ZHCSOP8A March   2022  – September 2023 TPS3760

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Device Comparison
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Timing Diagrams
    8. 7.8 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Voltage (VDD)
        1. 8.3.1.1 Undervoltage Lockout (VPOR < VDD < UVLO)
        2. 8.3.1.2 Power-On Reset (VDD < VPOR )
      2. 8.3.2 SENSE
        1. 8.3.2.1 SENSE Hysteresis
      3. 8.3.3 Output Logic Configurations
        1. 8.3.3.1 Open-Drain
        2. 8.3.3.2 Push-Pull
        3. 8.3.3.3 Active-High (RESET)
        4. 8.3.3.4 Active-Low (RESET)
      4. 8.3.4 User-Programmable Reset Time Delay
        1. 8.3.4.1 Reset Time Delay Configuration
      5. 8.3.5 User-Programmable Sense Delay
        1. 8.3.5.1 Sense Time Delay Configuration
      6. 8.3.6 Manual RESET (CTR / MR) Input
      7. 8.3.7 RESET Latch Mode
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Adjustable Voltage Thresholds
    3. 9.3 Typical Application
      1. 9.3.1 Design 1: Off-Battery Monitoring
        1. 9.3.1.1 Design Requirements
        2. 9.3.1.2 Detailed Design Procedure
        3. 9.3.1.3 Application Curves
  11. 10Power Supply Recommendations
    1. 10.1 Power Dissipation and Device Operation
  12. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Creepage Distance
  13. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 静电放电警告
    6. 12.6 术语表
  14. 13Mechanical, Packaging, and Orderable Information

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7.6 Timing Requirements

At VDD(MIN) ≤ VDD ≤ VDD(MAX), CTR/MR = CTS = open (1), output reset pull-up resistor RPU = 10 kΩ, voltage VPU = 5.5V, and CLOAD = 10 pF. VDD and SENSE slew rate = 1V / µs. The operating free-air temperature range TA = – 40°C to 125°C, unless otherwise noted. Typical values are at TA = 25°C and VDD = 16 V and VIT = 6.5 V (VIT refers to either VITN or VITP).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Common timing parameters
tCTR Reset release time delay
(CTR/MR) (2)		 VIT = 2.7 V to 36 V
CCTR = Open
20% Overdrive from Hysteresis		 100 µs
VIT = 800 mV
CCTR = Open
20% Overdrive from Hysteresis		 40 µs
tCTS Sense detect time delay 
(CTS) (3)		 VIT = 2.7 V to 36 V
CCTS = Open
20% Overdrive from VIT		 34 90 µs
VIT = 800 mV
CCTS = Open
20% Overdrive from VIT		 8 17 µs
tSD Startup Delay (4) CCTR/MR = Open
 		 2 ms
(1) CCTR = Reset delay channel
CCTS = Sense delay channel
(2) CTR Reset detect time delay:
Overvoltage active-LOW output is measure from VITP - HYS  to VOH
Undervoltage active-LOW output is measure from VITN + HYS  to VOH
Overvoltage active-HIGH output is measure from VITP - HYS  to VOL
Undervoltage active-HIGH output is measure from VITN + HYS  to VOL
(3) CTS Sense detect time delay:
Active-low output is measure from VIT to VOL (or VPullup)
Active-high output is measured from VIT to VOH 
VIT refers to either VITN or VITP
(4) During the power-on sequence, VDD must be at or above VDD (MIN) for at least tSD before the output is in the correct state based on VSENSE. 
tSD time includes the propagation delay (CCTR = Open). Capaicitor on CCTR will add time to tSD. 
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