ZHCSDS9 April   2015 TPS3779 , TPS3780

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
  4. 修订历史记录
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Inputs (SENSE1, SENSE2)
      2. 8.3.2 Outputs (OUT1, OUT2)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation (VDD ≥ VDD(min))
      2. 8.4.2 Power-On Reset (VDD < V(POR))
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Threshold Overdrive
      2. 9.1.2 Sense Resistor Divider
    2. 9.2 Typical Applications
    3. 9.3 Monitoring Two Separate Rails
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curve
    4. 9.4 Early Warning Detection
      1. 9.4.1 Design Requirements
      2. 9.4.2 Detailed Design Procedure
      3. 9.4.3 Application Curve
  10. 10Power-Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 器件支持
      1. 12.1.1 开发支持
        1. 12.1.1.1 评估模块
        2. 12.1.1.2 Spice 模型
      2. 12.1.2 器件命名规则
    2. 12.2 文档支持
      1. 12.2.1 相关文档
        1. 12.2.1.1 相关文档 
    3. 12.3 相关链接
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 术语表
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Power-Supply Recommendations

The TPS3779 and TPS3780 are designed to operate from an input voltage supply range between 1.5 V and
6.5 V. An input supply capacitor is not required for this device; however, good analog practice (required for less VDD < 1.5 V) is to place a 0.1-µF or greater capacitor between the VDD pin and the GND pin. This device has a 7-V absolute maximum rating on the VDD pin. If the voltage supply providing power to VDD is susceptible to any large voltage transient that can exceed 7 V, additional precautions must be taken.

For applications where SENSE is greater than 0 V before VDD, and subject to a startup slew rate of less than 200 mV per 1 ms, the output can be driven to logic high in error. To correct the output, cycle the SENSE lines below VIT– or sequence SENSE after VDD.