Make sure that the connection to the VDD pin is low impedance. Good analog
design practice is to place a greater than 0.1 µF
ceramic capacitor as near as possible to the VDD
pin.
To further improve the noise immunity on the
SENSEx pins, placing a 1 nF to 10 nF capacitor
between the SENSEx pins and GND can reduce the
sensitivity to transient voltages on the monitored
signal.
If a capacitor is used on CTS1, CTS2, CTR1, or CTR2, place these components as
close as possible to the respective pins. If the
capacitor adjustable pins are left unconnected,
make sure to minimize the amount of parasitic
capacitance on the pins to less than 5 pF.
For open-drain variants, place the pull-up resistors on
RESET1 and
RESET2 pins as close to the
pins as possible.
When laying out metal traces,
separate high voltage traces from low voltage traces as much as possible. If
high and low voltage traces need to run close by, spacing between traces should
be greater than 20 mils (0.5 mm).
Do not have high voltage metal
pads or traces closer than 20 mils (0.5 mm) to the low voltage metal pads or
traces.