SBVS085J January   2007  – June 2017

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Immunity to SENSE Pin Voltage Transients
      2. 8.3.2 SENSE Input
      3. 8.3.3 Manual Reset (MR) Input
      4. 8.3.4 Selecting the Reset Delay Time
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Related Links
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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7 Specifications

7.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD Input voltage –0.3 7 V
VCT CT voltage –0.3 (VDD + 0.3) V
VMR,
VRESET,
VSENSE 		MR, RESET, SENSE voltage –0.3 7 V
IRESET RESET pin current 5 mA
TJ Operating junction temperature(2) –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under the Electric Characteristics is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Due to the low dissipated power in this device, it is assumed that TJ = TA.

7.2 ESD Ratings

VALUE UNIT
TPS3808G125QDBVRQ1 IN SOT-23 PACKAGE
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V
Charged device model (CDM), per AEC Q100-011 ±1000
Machine Model (MM) ±50
TPS3808GXX-Q1 IN SOT-23 PACKAGE
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V
Charged device model (CDM), per AEC Q100-011 ±500
TPS3808G01QDRVRQ1 IN SON PACKAGE
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V
Charged device model (CDM), per AEC Q100-011 ±500
Machine Model (MM) ±50
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD input supply 1.8 6.5 V
VSENSE SENSE pin voltage 0 VDD V
MR Manual reset pin voltage 0 VDD V

7.4 Thermal Information

THERMAL METRIC(1) TPS3808Gxx-Q1 UNIT
DBV (SOT-23) DRV (WSON)
6 PINS 6 PINS
RθJA Junction-to-ambient thermal resistance 180.9 178.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 117.8 95.6 °C/W
RθJB Junction-to-board thermal resistance 27.8 135 °C/W
ψJT Junction-to-top characterization parameter 18.9 6.3 °C/W
ψJB Junction-to-board characterization parameter 27.3 136.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 7.3 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

1.8 V ≤ VDD ≤ 6.5 V, RLRESET = 100 kΩ, CLRESET = 50 pF, over operating temperature range (TJ = –40°C to +125°C) (unless otherwise noted), typical values at TJ = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VDD Input supply range 1.8 6.5 V
IDD Supply current (into VDD pin) VDD = 3.3 V, RESET not asserted, MR, RESET, CT open 2.4 5 μA
VDD = 6.5 V, RESET not asserted, MR, RESET, CT open 2.7 6
VOL Low-level output voltage 1.3 V ≤ VDD < 1.8 V, IOL = 0.4 mA 0.3 V
1.8 V ≤ VDD ≤ 6.5 V, IOL = 1 mA 0.4
Power-up reset voltage(1) VOL (max) = 0.2 V, I RESET = 15 μA 0.8 V
VIT Negative-going input threshold accuracy TPS3808G01-Q1 –2% ±1% 2%
VIT ≤ 3.3 V –1.5% ±0.5% 1.5%
3.3 V < VIT ≤ 5 V –2% ±1% 2%
VIT ≤ 3.3 V –40°C < TJ < 85°C –1.25% ±0.5% 1.25%
3.3 V < VIT ≤ 5 V –1.5% ±0.5% 1.5%
VHYS Hysteresis on VIT pin TPS3808G01-Q1 1.5 3 %VIT
–40°C < TJ < 85°C 1 2
1 2.5
R MR MR internal pullup resistance VSENSE = VIT 70 90 kΩ
ISENSE Input current at SENSE pin TPS3808G01-Q1 –25 25 nA
VSENSE = 6.5 V 1.7 μA
IOH RESET leakage current V RESET = 6.5 V, RESET not asserted 300 nA
CIN Input capacitance, any pin CT pin VIN = 0 V to VDD 5 pF
Other pins VIN = 0 V to 6.5 V 5
VIL MR logic low input 0 0.3 VDD V
VIH MR logic high input 0.7 VDD VDD V
(1) Power-up reset voltage is the lowest supply voltage (VDD) at which RESET becomes active (trise(VDD) ≥ 15 μs/V).

7.6 Timing Requirements

MIN NOM MAX UNIT
td RESET delay time CT = Open See Figure 1 12 20 28 ms
CT = VDD 180 300 420
CT = 100 pF 0.75 1.25 1.75
CT = 180 nF 0.7 1.2 1.7 s
tpHL Propagation delay MR to RESET VIH = 0.7 VDD, VIL = 0.3 VDD 150 ns
High-level to low-level RESET delay SENSE to RESET VIH = 1.05 VIT, VIL = 0.95 VIT 20 μs
tw Maximum transient duration SENSE VIH = 1.05 VIT, VIL = 0.95 VIT 20 μs
MR VIH = 0.7 VDD, VIL = 0.3 VDD 0.001
TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1 TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1 td_tps3803_bvs050.gif Figure 1. MR and SENSE Reset Timing Diagram

7.7 Typical Characteristics

At TJ = 25°C, VDD = 3.3 V, RLRESET = 100 kΩ, and CLRESET = 50 pF (unless otherwise noted)
TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1 TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1 vdo_v_ta_bvs050.gif
Figure 2. Normalized RESET Time-out Period vs Temperature (CT = Open, CT = VDD, CT = Any)
TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1 TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1 ignd_v_io_bvs085.gif
Figure 4. Low-Level RESET Voltage vs RESET Current
TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1 TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1 vo_hsto_dft_bvs050.gif
Figure 3. Normalized Sense Threshold Voltage (VIT) vs Temperature
TPS3808G01-Q1 TPS3808G12-Q1 TPS3808G125-Q1 TPS3808G15-Q1 TPS3808G18-Q1 TPS3808G30-Q1 TPS3808G33-Q1 TPS3808G50-Q1 ignd_v_ta_bvs085.gif
Figure 5. Low-Level RESET Voltage vs RESET Current
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