The TPS3808 has three options for setting the RESET delay time as shown in Figure 8-2. Figure 8-2 (a) shows the configuration for a fixed 300-ms typical delay time by tying C_T to V_DD; a resistor from 40 kΩ to 200 kΩ must be used. Supply current is not affected by the choice of resistor. Figure 8-2 (b) shows a fixed 20-ms delay time by leaving the C_T pin open. Figure 8-2 (c) shows a ground referenced capacitor connected to C_T for a user-defined program time between 1.25 ms and 10 s.

Figure 8-2 Configuration Used to Set the RESET Delay Time

The capacitor C_T should be ≥ 100 pF nominal value in order for the TPS3808xxx to recognize that the capacitor is present. The capacitor value for a given delay time can be calculated using Equation 1.

Equation 1.

The reset delay time is determined by the time it takes an on-chip precision 220-nA current source to charge the external capacitor to 1.23 V. When a RESET is asserted, the capacitor is discharged. When the RESET conditions are cleared, the internal current source is enabled and begins to charge the external capacitor. When the voltage on this capacitor reaches 1.23 V, RESET is deasserted. Note that a low-leakage type capacitor such as a ceramic should be used, and that stray capacitance around this pin may cause errors in the reset delay time.