The manual reset ( MR) input allows a processor or other logic circuits to initiate a reset. A logic low (0.3 V_DD) on MR causes RESET to assert. After MR returns to a logic high and SENSE is above its reset threshold, RESET is de-asserted after the user-defined reset delay expires. Note that MR is internally tied to V_DD using a 90-kΩ resistor, so this pin can be left unconnected if MR is not used.

See Figure 8-3 for how MR can be used to monitor multiple system voltages. Note that if the logic signal driving MR does not go fully to V_DD, there is some additional current draw into V_DD as a result of the internal pullup resistor on MR. To minimize current draw, a logic-level FET can be used as illustrated in Figure 8-4.

Figure 8-3 Using MR to Monitor Multiple System Voltages

Figure 8-4 Using an External MOSFET to Minimize I_DD When MR Signal Does Not Go to V_DD