When VDD is greater than VDD(min), the
RESET signal is determined by the voltage on the SENSE pin and the logic state of
MR.
- MR high: When the voltage on VDD is greater than 1.7 V for a time of the selected tD, the
RESET signal corresponds to the voltage on SENSE relative to VIT.
- MR low: in this mode,
RESET is held low regardless of the value of the SENSE pin.