ZHCSM34M May 2004 – March 2023 TPS3808
PRODUCTION DATA
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Device Voltage Thresholds
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封装选项
机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
- DRV|6
订购信息
6 Pin Configuration and Functions
Figure 6-1 DBV Package6-Pin SOT-23Top View
Figure 6-2 DRV Package6-Pin (2.00 mm × 2.00 mm) WSON With Thermal PadTop ViewTable 6-1 Pin Functions
| PIN | I/O | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | SOT-23 | WSON | ||
| CT | 4 | 3 | I | Reset period programming pin. Connecting this pin to VDD through a 40-kΩ to 200-kΩ resistor or leaving it open results in fixed delay times (see Section 7.5). Connecting this pin to a ground referenced capacitor ≥ 100 pF gives a user-programmable delay time. See Section 8.3.2 for more information. |
| GND | 2 | 5 | — | Ground |
| MR | 3 | 4 | I | Driving the manual reset pin ( MR) low asserts RESET. MR is internally tied to VDD by a 90-kΩ pull-up resistor. |
| RESET | 1 | 6 | O | RESET is an open-drain output that is driven to a low-impedance state when RESET is asserted (either the SENSE input is lower than the threshold voltage (VIT) or the MR pin is set to a logic low). RESET remains low (asserted) for the reset period after both SENSE is above VIT and MR is set to a logic high. A pull-up resistor from 10 kΩ to 1 MΩ should be used on this pin, and allows the reset pin to attain voltages higher than VDD. |
| SENSE | 5 | 2 | I | This pin is connected to the voltage to be monitored. If the voltage at this terminal drops below the threshold voltage VIT, then RESET is asserted. |
| VDD | 6 | 1 | I | Supply voltage. It is good analog design practice to place a 0.1-μF ceramic capacitor close to this pin. |
| Thermal Pad | — | Pad | — | Thermal Pad. Connect to ground plane to enhance thermal performance of package. |