RESET remains high (unasserted) as long as SENSE is above its threshold (V_IT) and the manual reset ( MR) is logic high. If either SENSE falls below V_IT or MR is driven low, RESET is asserted, driving the RESET pin to a low impedance.

Once MR is again logic high and SENSE is above V_IT + V_HYS (the threshold hysteresis), a delay circuit is enabled that holds RESET low for a specified reset delay period. Once the reset delay has expired, the RESET pin goes to a high impedance state. The pullup resistor from the open-drain RESET to the supply line can be used to allow the reset signal for the microprocessor to have a voltage higher than V_DD (up to 6.5 V). The pullup resistor should be no smaller than 10 kΩ as a result of the finite impedance of the RESET line.