ZHCSKC4H May   2008  – October 2021

PRODMIX  

  1. 1 特性
  2. 2 应用
  3. 3 描述
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Timing Diagrams
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 VDD Hysteresis
        2. 7.3.1.2 VDD Glitch Immunity
      2. 7.3.2 Implemented Window-Watchdog Settings
        1. 7.3.2.1 Timing Rules of Window-Watchdog
      3. 7.3.3 Watchdog Software Considerations
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Lower-Boundary Calculation
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Programming Window-Watchdog Using an External Capacitor
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 术语表
  12. 12Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

7.1 Overview

The TPS3813-Q1 devices (TPS3813K33-Q1 and TPS3813I50-Q1) are a family of supervisory circuits with watchdog functionality. The TPS3813-Q1family of devices is designed to assert a reset on the RESET pin when the supply (VDD) drops below the threshold voltage (VIT) which varies depending on which device is used. When the VDD supply rises above 1.1 V, the RESET pin output state becomes valid and is active in logic low state until the VDD supply crosses the voltage threshold (VIT + VHYS). The watchdog window can be programmed using the WDT and WDR pins with several different configurations, all of which are explained in the following sections.
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