These devices are immune to quick voltage transient or excursion on VDD. Sensitivity to transients depends on both pulse duration (t_{GI_VIT}) found in Section 6.6 and transient overdrive. Overdrive is defined by how much VDD exceeds the specified threshold. Threshold overdrive is calculated as a percent of the threshold in question, as shown in Equation 1.

where

• V_IT = V_IT– is the threshold voltage
• V_IT+ = V_IT + V_HYS is the rising threshold voltage
• VDD is the input voltage crossing V_IT

Figure 7-1 Overdrive Versus Pulse Duration

TPS3813-Q1 devices have built-in glitch immunity (t_{GI_VIT-}) as shown in Section 6.6. Figure 7-1 shows that VDD must fall below V_IT for t_{GI_VIT}, otherwise the faling transistion is ignored. When VDD falls below V_IT for t_{GI_VIT}, RESET transitions low to indicate a fault condition after the propagation delay high-to-low (t_PHL). When VDD rises above V_IT+ = V_IT + V_HYS, RESET deasserts to a logic high indicating there is no more fault condition only if VDD remains above V_IT+ for longer than the reset delay (t_D).