The TPS3813xxx family of supervisory circuits provide circuit initialization and timing supervision signals. During power on, RESET is asserted (low) when the supply voltage (V_DD) increases above 1.1V. Thereafter, the supervisory circuit monitors V_DD and keeps RESET low as long as V_DD remains below the threshold voltage (V_IT). Once V_DD increases above V_IT, an internal timer delays the deassertion of the output to allow for a proper system reset before RESET transitions to a high state. The delay time (t_d) is 25ms typical and starts after V_DD rises above the V_IT. When the supply voltage drops below V_IT, the output transitions low again. All the devices of this family have a fixed threshold voltage set by an internal voltage divider.

The TPS3813xxx family incorporates a so-called window-watchdog timer, which has a programmable delay and window ratio. The supervised processor must trigger the WDI pin of the TPS3813xxx within the user-programmable window to keep RESET from asserting. The upper limit of the watchdog time-out can be set by either connecting WDT to GND, V_DD, or using an external capacitor. The lower limit and thus the window ratio is set by connecting WDR to GND or V_DD.