SLVS331J December   2000  – August 2024 TPS3813

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Dissipation Ratings
    9. 6.9 Typical Characteristics
  8. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Voltage (VDD)
        1. 7.3.1.1 VDD Hysteresis
        2. 7.3.1.2 VDD Glitch Immunity
      2. 7.3.2 User-Programmable Watchdog Timer (WDI)
      3. 7.3.3 RESET Output
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation (VDD > VIT)
      2. 7.4.2 Above Power-On Reset But Less Than Threshold (VPOR < VDD < VIT)
      3. 7.4.3 Below Power-On Reset (VDD < VPOR)
    5. 7.5 Programming
      1. 7.5.1 Implementing Window-Watchdog Settings
      2. 7.5.2 Programmable Window-Watchdog by Using an External Capacitor
      3. 7.5.3 Lower Boundary Calculation
      4. 7.5.4 Watchdog Software Considerations
      5. 7.5.5 Power-Up Considerations
  9. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. Device and Documentation Support
    1. 9.1 Related Links
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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Implementing Window-Watchdog Settings

There are two ways to configure the watchdog timer window the most flexible is to connect a capacitor to WDT to set the upper boundary of the window watchdog while connecting WDR to either VDD or GND, thus setting the lower boundary. The other way to configure the timing is by wiring the WDT and WDR pin to either VDD or GND. By hard-wiring the pins to either VDD or GND there are four different timings available; these settings are listed in Table 7-2.

Table 7-2 Cap-Free Timer Settings
SELECTED OPERATION MODEWINDOW FRAMELOWER WINDOW FRAME
WDT = 0VWDR = 0VMax = 0.3sMax = 9.46ms
Typ = 0.25sTyp = 7.86ms
Min = 0.2sMin = 6.27ms
WDR = VDDMax = 0.3sMax = 2.43ms
Typ = 0.25sTyp = 2ms
Min = 0.2sMin = 1.58ms
WDT = VDDWDR = 0VMax = 3sMax = 93.8ms
Typ = 2.5sTyp = 78.2ms
Min = 2sMin = 62.5ms
WDR = VDDMax = 3sMax = 23.5ms
Typ = 2.5sTyp = 19.6ms
Min = 2sMin = 15.6ms

To visualize the values named in the table, a timing diagram was prepared. It is used to describe the upper and lower boundary settings. For an application, the important boundaries are the tboundary,max and twindow,min. Within these values, the watchdog timer must be retriggered to avoid a time-out condition or a boundary violation in the event of a trigger pulse in the lower boundary. The values in the table above are typical and worst-case conditions and are valid over the whole temperature range of –40°C to +85°C.

The shaded areas shown in Figure 7-2 are cases where undefined operation can happen. This device can not detect a violation if a WDI pulse occurs within these three shaded areas. The first shaded area addresses the situation of two consecutive rising edges occur within a quick amount of time. The typical time between rising edges must be more than 500µs. The second and third shaded areas are defined by the min and max variance of the lower boundary (tboundary) and upper boundary ( twindow). Set the WDI rising edge within the tboundary,max and twindow,min for correct operation.

TPS3813 Upper and
                    Lower Boundary Visualization Figure 7-2 Upper and Lower Boundary Visualization