8.1 Overview

The TPS382x-xx-Q1 family of supervisors provide circuit initialization and timing supervision. Optional configurations include devices with active-high and active-low output signals (TPS3824/5-xx-Q1), devices with a watchdog timer (TPS3820/3/4/8-xx-Q1), and devices with manual reset (MR) pins (TPS3820/3/5/8-xx-Q1). RESET asserts when the supply voltage, V_DD, rises above 1.1 V. For devices with active-low output logic, the device monitors V_DD and keeps RESET low as long as V_DD remains below the negative threshold voltage, V_IT−. For devices with active-high output logic, RESET remains high as long as V_DD remains below V_IT−. An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, t_d, starts after V_DD rises above the positive threshold voltage (V_IT− + V_HYS). When the supply voltage drops below V_IT−, the output becomes active (low) again. All the devices of this family have a fixed-sense threshold voltage, V_IT–, set by an internal voltage divider, so no external components are required.

The TPS382x-xx-Q1 family is designed to monitor supply voltages of 2.5 V, 3 V, 3.3 V, and 5 V. The devices are available in a 5-pin SOT-23 package and are characterized for operation over a temperature range of −40°C to 125°C, and are qualified in accordance with AEC-Q100 stress test qualification for integrated circuits.