SLVS292F June 2000 – September 2019 TPS3836 , TPS3837 , TPS3838
PRODUCTION DATA.
The VDD pin monitors the input voltage with an internal comparator and when the voltage at VDD falls below VIT, the reset output is asserted to active state after the propagation delay time: tPHL for TPS3836 and TPS3838, tPLH for TPS3837. When VDD rises above VIT plus VHYS and MR is logic high, the reset output deasserts to an inactive state after the reset delay time, tD. Note that the VDD and MR pins have different propagation delays with the same label.