8.3.4.2 RESET Output, Active-High

RESET (active-high), denoted with no bar above the pin label, applies only to TPS3840PH-Q1 push-pull active-high version. RESET remains low (deasserted) as long as VDD is above the threshold (V_IT-) and the manual reset signal (MR) is logic high or floating. If VDD falls below the negative threshold (V_IT-) or if MR is driven low, then RESET is asserted driving the RESET pin to high voltage (V_OH).

When MR is again logic high and VDD is above V_IT+ the delay circuit will hold RESET high for the specified reset time delay (t_D). When the reset time delay has elapsed, the RESET pin goes back to low voltage (V_OL ).