9.2.1.2 Detailed Design Procedure

The primary constraint for this application is choosing the correct device to monitor the supply voltage of the microprocessor. The TPS3840-Q1 can monitor any voltage between 1.6 V and 10 V and is available in 0.1 V increments. Depending on how far away from the nominal voltage rail the user wants the voltage supervisor to trigger determines the correct voltage supervisor variant to choose. In this example, the first TPS3840-Q1 triggers when the 3.3-V rail falls to 3.0 V. The second TPS3840-Q1 triggers a reset when the 1.8-V rail falls to 1.6 V. The secondary constraint for this application is the reset time delay that must be at least 25 ms to allow the microprocessor, and all other devices using the 3.3-V rail, enough time to startup correctly before the 1.8-V rail is enabled via the LDO. Because a minimum time is required, the user must account for capacitor tolerance. For applications with ambient temperatures ranging from –40°C to +125°C, C_CT can be calculated using R_CT and solving for C_CT in Equation 2. Solving Equation 2 for 25 ms gives a minimum capacitor value of 0.04 µF which is rounded up to a standard value 0.047 µF to account for capacitor tolerance.

A 1-µF decoupling capacitor is connected to the VDD pin as a good analog design practice. The pull-up resistor is only required for the Open-Drain device variants and is calculated to maintain the RESET current within the ±5 mA limit found in the Recommended Operating Conditions: R_Pull-up = V_Pull-up ÷ 5 mA. For this design, a standard 10-kΩ pull-up resistor is selected to minimize current draw when RESET is asserted. Keep in mind the lower the pull-up resistor, the higher V_OL. The MR pin can be connected to an external signal if desired or left floating if not used due to the internal pull-up resistor to VDD.