11.1 Layout Guidelines

Make sure that the connection to the VDD pin is low impedance. Good analog design practice recommends placing a minimum 0.1-µF ceramic capacitor as near as possible to the VDD pin. If a capacitor is not connected to the CT pin, then minimize parasitic capacitance on this pin so the rest time delay is not adversely affected.

• Make sure that the connection to the VDD pin is low impedance. Good analog design practice is to place a >0.1-µF ceramic capacitor as near as possible to the VDD pin.
• If a C_CT capacitor is used, place these components as close as possible to the CT pin. If the CT pin is left unconnected, make sure to minimize the amount of parasitic capacitance on the pin to <5 pF.
• Place the pull-up resistors on RESET pin as close to the pin as possible.