The RESET pin features a programmable reset delay time that can be adjusted from 703 µs to 3.22 seconds when using adjustable capacitor timing. RESET is an open-drain output that should be pulled up through a 1-kΩ to 100-kΩ pullup resistor. When V_DD is above V_DD(min), RESET remains high (not asserted) when the SENSE voltage is between the positive threshold (V_IT+(OV)) and the negative threshold (V_IT-(UV)). If SENSE falls below
V_IT-(UV) or rises above V_IT+(OV), then RESET is asserted, driving the RESET pin to a low-impedance state. When SENSE comes back into the valid window, a RESET delay circuit is enabled that holds RESET low for a specified reset delay period (t_RST). This t_RST period is determined by what is connected to the CRST pin; see Figure 8-1. When the reset delay has elapsed, the RESET pin goes to a high-impedance state and uses a pullup resistor to hold RESET high. The pullup resistor must be connected to the proper voltage rail to allow other devices to be connected at the correct interface voltage. To ensure proper voltage levels, give some consideration when choosing the pullup resistor values. The pullup resistor value is determined by output logic low voltage (V_OL), capacitive loading, and leakage current (I_D); see the Section 8.1.1 section for more information.