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ZHCSFP1A November 2016 – September 2021 TPS3851

PRODUCTION DATA

封装选项

机械数据 (封装 | 引脚)

DRB|8
- MPDS118K

散热焊盘机械数据 (封装 | 引脚)

DRB|8
- QFND058N

订购信息

6.6 Timing Requirements

at V_ITN + V_HYST ≤ V_DD ≤ 6.5 V over the operating temperature range of –40°C ≤ T_A, T _A ≤ 125°C (unless otherwise noted); the open-drain pullup resistors are 10 kΩ for each output; typical values are at T_A = 25°C

			MIN	NOM	MAX	UNIT
GENERAL
t_INIT	CWD pin evaluation period ⁽¹⁾			381		µs
	Minimum MR, SET1 pin pulse duration			1		µs
	Startup delay ⁽²⁾			300		µs
RESET FUNCTION
t_RST	Reset timeout period		170	200	230	ms
t_RST-DEL	V_DD to RESET delay	V_DD = V_ITN + V_HYST + 2.5%		35		µs
t_RST-DEL	V_DD to RESET delay	V_DD = V_ITN – 2.5%		17		µs
t_MR-DEL	MR to RESET delay			200		ns
WATCHDOG FUNCTION
t_WD	Watchdog timeout ⁽³⁾	CWD = NC, SET1 = 0 ⁽⁴⁾	Watchdog disabled
		CWD = NC, SET1 = 1 ⁽⁴⁾	1360	1600	1840	ms
		CWD = 10 kΩ to VDD, SET1 = 0 ⁽⁴⁾	Watchdog disabled
		CWD = 10 kΩ to VDD, SET1 = 1 ⁽⁴⁾	170	200	230	ms
t_WD-setup	Setup time required for device to respond to changes on WDI after being enabled			150		µs
	Minimum WDI pulse duration			50		ns
t_WD-del	WDI to WDO delay			50		ns

(1) Refer to Section 8.1.1.2

(2) During power-on, V_DD must be a minimum 1.6 V for at least 300 µs before RESET correlates with V_DD

(3) The fixed watchdog timing covers both standard and extended versions.

(4) SET1 = 0 means V_SET1 < V_IL; SET1 = 1 means V_SET1 > V_IH.