8.1.1.1 Factory-Programmed Timing Options

If using the factory-programmed timing options (listed in Table 2), the CWD pin must either be unconnected or pulled up to VDD through a 10-kΩ pullup resistor. Using these options enables high-precision watchdog timing.

8.1.1.2 Adjustable Capacitor Timing

Adjustable capacitor timing is achievable by connecting a capacitor to the CWD pin. If a capacitor is connected to CWD, then a 375-nA current source charges C_CWD until V_CWD = 1.21 V. The TPS3852-Q1 determines the window watchdog upper boundary with the formula given in Equation 1, where C_CWD is in microfarads (µF) and t_WDU is in seconds.

The TPS3852-Q1 is limited to using C_CWD capacitors between 100 pF and 1 µF. Note that Equation 1 is for ideal capacitors; capacitor tolerances cause the actual device timing to vary. For the most accurate timing, use ceramic capacitors with COG dielectric material. As shown in Table 3, when using the minimum capacitance of 100 pF, the watchdog upper boundary is 62.74 ms; whereas with a 1-µF capacitance, the watchdog upper boundary is 77.455 seconds. If a C_CWD capacitor is used, Equation 1 can be used to set the window watchdog upper boundary (t_WDU). Table 4 shows how t_WDU can be used to calculate t_WDL.

Table 3. t_WDU Values for Common Ideal Capacitor Values

Table 4. Programmable CWD Timing

8.2.2.1 Monitoring the 3.3-V Rail

This application calls for very tight monitoring of the rail with only 5% of variation allowed on the rail. To ensure this requirement is met, the TPS3852G33-Q1 was chosen for its –4% threshold. To calculate the worst-case for V_ITN, the accuracy must also be taken into account. The worst-case for V_ITN can be calculated by Equation 3:

8.2.2.2 Calculating RESET and the WDO Pullup Resistor

The TPS3852-Q1 uses an open-drain configuration for the RESET circuit, as shown in Figure 21. When the FET is off, the resistor pulls the drain of the transistor to VDD and when the FET is turned on, the FET attempts to pull the drain to ground, thus creating an effective resistor divider. The resistors in this divider must be chosen to ensure that V_OL is below the maximum value. To choose the proper pullup resistor, there are three key specifications to keep in mind: the pullup voltage (V_PU), the recommended maximum RESET pin current (I_RESET), and V_OL. The maximum V_OL is 0.4 V, meaning that the effective resistor divider created must be able to bring the voltage on the reset pin below 0.4 V with I_RESET kept below 10 mA. For this example, with a V_PU of 3.3 V, a resistor must be chosen to keep I_RESET below 50 μA because this value is the maximum consumption current allowed. To ensure this specification is met, a pullup resistor value of 100 kΩ was selected, which sinks a maximum of 33 μA when RESET or WDO is asserted. As illustrated in Figure 11, when the RESET current is at 33 μA the low-level output voltage is approximately zero.

Figure 21. RESET Open-Drain Configuration

8.2.2.3 Setting the Window Watchdog

As illustrated in Figure 18, there are three options for setting the window watchdog. The design specifications in this application require the programmable timing option (external capacitor connected to CWD). When a capacitor is connected to the CWD pin, the window is governed by Equation 4. Equation 4 is only valid for ideal capacitors, any temperature or voltage derating must be accounted for separately.

Equation 4.

The nearest standard capacitor value to 2.5 nF is 2.2 nF. Selecting 2.2 nF for the C_CWD capacitor gives the following minimum and maximum timing parameters:

Equation 5.

Equation 6.

Capacitor tolerance also influence t_WDU(MIN) and t_WDL(MAX). Select a ceramic COG dielectric capacitor for high accuracy. For 2.2 nF, COG capacitors are readily available with a 5% tolerance, which results in a 5% decrease in t_WDU(MIN) and a 5% increase in t_WDL(MAX), giving 181 ms and 135 ms, respectively. A falling edge must be issued within this window.

8.2.2.4 Watchdog Disabled During Initialization Period

The watchdog is often needed to be disabled during startup to allow for an initialization period. When the initialization period is over, the watchdog timer is turned back on to allow the microcontroller to be monitored by the TPS3852-Q1. To achieve this setup, SET1 must start at GND. In this design, SET1 is controlled by a TPS3890-Q1 supervisor. In this application, the TPS3890-Q1 was chosen to monitor V_DD as well, meaning that RESET on the TPS3890-Q1 stays low until V_DD rises above V_ITN. When V_DD comes up, the delay time can be adjusted through the CT capacitor on the TPS3890-Q1. With this approach, the RESET delay can be adjusted from a minimum of 25 µs to a maximum of 30 seconds. For this design, a minimum delay of 7 seconds is needed until the watchdog timer is enabled. The CT capacitor calculation (see the TPS3890-Q1 data sheet) yields an ideal capacitance of 6.59 µF, giving a closest standard ceramic capacitor value of 6.8 µF. When connecting a 6.8-µF capacitor from CT to GND, the typical delay time is 7.21 seconds. Figure 22 illustrates the typical startup waveform for this circuit when the watchdog input is off. Figure 22 illustrates that when the watchdog is disabled, the WDO output remains high. See the TPS3890-Q1 data sheet for detailed information on the TPS3890-Q1.