ZHCSQB8C July   2021  – December 2022 TPS38700-Q1

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device State Diagram
      2. 8.3.2 Built-In Self Test and Configuration Load
      3. 8.3.3 CLK32K
      4. 8.3.4 BACKUP State
      5. 8.3.5 FAILSAFE State
      6. 8.3.6 Transitioning Sequences
        1. 8.3.6.1 Sequence 1: Power Up
        2. 8.3.6.2 Sequence 2: Emergency Power Down
        3. 8.3.6.3 Sequence 3: Sleep Entry
        4. 8.3.6.4 Sequence 4: Sleep Exit
        5. 8.3.6.5 Sequence 5 & 6: Power Down from Active and Sleep States
        6. 8.3.6.6 Sequence 7: Sleep Exit Due to NRST_IN
        7. 8.3.6.7 Sequence 8: RESET Due to NRST_IN
        8. 8.3.6.8 Sequence 9: Failsafe Power Down
        9. 8.3.6.9 Output Sequencing
      7. 8.3.7 I2C
    4. 8.4 Register Map Table
      1. 8.4.1 Register Descriptions
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Automotive Multichannel Sequencer and Monitor
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power Supply Guidelines
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
      1.      Mechanical, Packaging, and Orderable Information

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9.2.2 Design Requirements

  • Eight different voltage rails supplied by DC/DC converters need to be properly sequenced in this design. The sequence order and timing requirements are outlined in Table 9-1 and Table 9-2.
  • Emergency power down functionality is optional.
  • Backup battery power supply required. This must be stepped down to a maximum value of 5.5 V in order to comply with the absolute maximum ratings of the VBBAT pin.
  • All detected failures in sequencing should be reported via an external hardware interrupt signal.
  • All detected failures should be logged in internal registers and be accessible to an external processor via I2C.

Table 9-1 Power Up and Power Down Sequence Requirement
ENABLE CHANNELPOWER UP SEQUENCE POSITIONPOWER DOWN SEQUENCE POSITIONTIME BETWEEN POWER UP SIGNALS (μs)TIME BETWEEN POWER DOWN SIGNALS (μs)
EN115625625
EN211625625
EN324625625
EN424625625
EN542625625
EN661625625
EN711625625
EN824625625
Table 9-2 Sleep Entry and Sleep Exit Sequence Requirement
ENABLE CHANNELSLEEP EXIT SEQUENCE POSITIONSLEEP ENTRY SEQUENCE POSITIONTIME BETWEEN SLEEP EXIT SIGNALS (μs)TIME BETWEEN SLEEP ENTRY SIGNALS (μs)
EN100625625
EN213625625
EN332625625
EN400625625
EN500625625
EN621625625
EN713625625
EN832625625
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