Built-In Self Test (BIST) is performed:

• AT POR, if TEST_CFG_AT_POR = 1

• When exiting Sequence 5 or Sequence 6, if TEST_CFG_AT_SHDN = 1 and the power down is not initiated by CTL_1. FORCE_SHDN[1:0] being set to 01b, 10b, or 11b.

Configuration load from OTP is assisted by ECC (supporting SEC-DED). This is to protect against data integrity issues and to maximize sysetem availability.

During BIST, NIRQ is de-asserted (asserted in case of failure), NRST is held low, ENx pins are held low (including pins with alternate functions), CLK32K is held low, input pins are ignored, and the I²C block is inactive with SDA and SCL de-asserted. Once BIST is completed without failure, I²C is immediately active and the device enters SHDN1 state after loading the configuration data from OTP. If BIST fails and/or ECC reports Double-Error Detection (DED), NIRQ is asserted, the device enters the FAILSAFE state (inputs are ignored), and a best effort attempt is made to active I²C. TEST_STAT register may provide additional information on the test results.