8.3.3 RESET Output

RESET remains high (deasserted) as long as SENSE is above the positive threshold (V_ITP) and the manual reset signal (MR) is logic high. If SENSE falls below the negative threshold (V_ITN) or if MR is driven low, then RESET is asserted, driving the RESET pin to a low impedance.

When MR is again logic high and SENSE is above V_ITP, a delay circuit is enabled that holds RESET low for a specified reset delay period (t_PD(r)). When the reset delay has elapsed, the RESET pin goes to a high-impedance state and uses a pullup resistor to hold RESET high. Connect the pullup resistor to the proper voltage rail to enable the outputs to be connected to other devices at the correct interface voltage level. RESET can be pulled up to any voltage up to 5.5 V, independent of the device supply voltage. To ensure proper voltage levels, give some consideration when choosing the pullup resistor values. The pullup resistor value is determined by V_OL, the output capacitive loading, and the output leakage current (I_LKG(OD)).