8.4.1 Normal Operation (VDD> VDD(min))
When VDD is greater than VDD(min), the RESET signal is determined by the voltage on the SENSE pin and the logic state of MR.
- MR high: when the voltage on VDD is greater than 1.5 V, the RESET signal corresponds to the voltage on the SENSE pin relative to the threshold voltage.
- MR low: in this mode, RESET is held low regardless of the voltage on the SENSE pin.