_{(1) tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to the CTR pin then tD programmed time
is added to the startup time.}

_{(2) Be advised, in some instances, the VDD falling slew rate in Figure 6-1 can be slow or such that VDD decay time is much larger than the SENSE
delay time (tD-SENSE) time allowing the output to assert. If the VDD falling slew rate is much faster than the (tD-SENSE), the output appears to be not
asserted.}

_{(1) tD (no cap) is included in tSTRT time delay. If tD delay is programmed by an external capacitor connected to the CTR pin then tD programmed time
is added to the startup time.}

_{(2) Be advised, in some instances, that the VDD falling slew rate in Figure 6-2 can be slow or such that VDD decay time is much larger than the SENSE
delay time (tD-SENSE) time allowing the output to assert. If the VDD falling slew rate is much faster than the (tD-SENSE), the output appears to be not
asserted.}