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符合汽车应用标准:
专为高性能而设计:
适用于多种应用:
多种输出拓扑/封装类型:
通过单独的 VDD 和 SENSE 引脚,可实现高可靠性系统所需的冗余。SENSE与VDD 解耦,可以监控VDD 以外的轨电压。SENSE 引脚的高阻抗输入支持使用可选的外部电阻器。CTS 和 CTR 都提供了对 RESET 信号的上升沿和下降沿进行延迟调整的能力。CTS 忽略受监控电压轨上的电压干扰,从而也可充当去抖动器;作为手动复位工作时,用于强制系统复位。
TPS3899-Q1 以紧凑的外形提供了精密的性能和卓越的功能,成为各种汽车和电池供电/低功耗应用的理想解决方案。该器件的额定工作温度范围为
–40°C 至 +125°C (TA)。
Figure 4-1 shows the device naming nomenclature of the TPS3899-Q1. For all possible output types and threshold voltage options, see Device Naming Convention for a more detailed explanation. Contact TI sales representatives or on TI's E2E forum for detail and availability of other options; minimum order quantities apply.
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NO. | NAME | ||
1 | CTR | — | Capacitor programmable reset delay: The CTR pin offers a user-adjustable delay time when returning from reset condition. Connecting this pin to a ground-referenced capacitor sets the RESET/RESET delay time to deassert. |
2 | CTS | — | Capacitor programmable sense delay: The CTS pin offers a user-adjustable delay time when asserting reset condition. Connecting this pin to a ground-referenced capacitor sets the RESET/RESET delay time to assert. |
3 | GND | — | Ground |
4 | VDD | I | Supply voltage pin: Good analog design practice is to place a 0.1µF decoupling capacitor close to this pin. |
5 | SENSE | I | This pin is connected to the voltage that
will be monitored for fixed variants or to a resistor divider for
the adjustable variant. When the voltage on the SENSE pin
transitions below the negative threshold voltage VIT-,
RESET/RESET asserts to active logic after
the sense delay set by CTS. When the voltage on the SENSE pin
transitions above the positive threshold voltage VIT- +
VHYS, RESET/RESET releases to
inactive logic (deasserts) after the reset delay set by CTR. For
noisy applications, placing a 10nF to 100nF ceramic capacitor close to this pin may be needed for optimum performance. |
6 | RESET | O | RESET active-low output that asserts to a logic low state after CTS delay when the monitored voltage on the SENSE pin is lower than the negative threshold voltage VIT-. RESET remains logic low (asserted) until the SENSE input rises above VIT- + VHYS and the CTR reset delay expires. |
6 | RESET | O | RESET active-high output that asserts to a logic high state after CTS delay when the monitored voltage on the SENSE pin is lower than the negative threshold voltage VIT-. RESET remains logic high (asserted) until the SENSE input rises above VIT- + VHYS and the CTR reset delay expires. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Voltage | VDD, SENSE, RESET (TPS3899DL) | –0.3 | 6.5 | V |
CTR, CTS, RESET (TPS3899PL), RESET (TPS3899PH) | –0.3 | VDD+0.3 (3) | V | |
Current | RESET pin and RESET pin | ±20 | mA | |
Temperature (2) | Operating ambient temperature, TA | –40 | 125 | °C |
Temperature (2) | Storage, Tstg | –65 | 150 |
VALUE | UNIT | ||||
---|---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per AEC Q100-002 (1) | ±2000 | V | |
Charged device model (CDM), per AEC Q100-011 | ±750 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
Voltage | VDD, SENSE, RESET (TPS3899DL) | 0 | 6 | V | |
Voltage | CTR, CTS, RESET (TPS3899PL), RESET (TPS3899PH) | 0 | VDD | V | |
Current | RESET pin and RESET pin current | 0 | ±5 | mA | |
TA | Operating free air temperature | –40 | 125 | °C | |
CCTR | CTR pin capacitor range | 0 | 10 | µF | |
CCTS | CTS pin capacitor range | 0 | 10 | µF |