When the voltage on V_DD is lower than V_POR, the device does not have enough voltage to assert the output RESET/RESET to the correct logic state. The output results in being undefined as shown in Figure 6-1 or in Figure 6-2. If the output RESET/RESET is an open-drain variant, the voltage can be pulled up to V_DD or to the pull-up voltage. Neither output can be relied upon for proper device function.