ZHCSKS5C September   2020  – January 2024 TPS3899

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison
  6.   Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 VDD Hysteresis
      2. 6.3.2 User-Programmable Sense and Reset Time Delay
      3. 6.3.3 RESET/RESET Output
      4. 6.3.4 SENSE Input
        1. 6.3.4.1 Immunity to SENSE Pin Voltage Transients
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation (VDD > VDD(min))
      2. 6.4.2 Above Power-On-Reset But Less Than VDD(min) (VPOR < VDD < VDD(min))
      3. 6.4.3 Below Power-On-Reset (VDD < VPOR)
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curves
      4. 7.2.4 Power Supply Recommendations
      5. 7.2.5 Layout
        1. 7.2.5.1 Layout Guidelines
        2. 7.2.5.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 支持资源
    4. 8.4 Trademarks
    5. 8.5 静电放电警告
    6. 8.6 术语表
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information

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7.2.1 Design Requirements

The design requirements, described in Table 7-1, for this design has a defined reset threshold voltage of 2.9V, a sense delay of 60ms, a reset delay of 60ms, and an output current no larger than 500µA.

Table 7-1 Design Requirements

PARAMETER

DESIGN REQUIREMENTS

DESIGN RESULTS

Reset Asserting

Reset needs to assert when under the reset condition of a button press or VDD ≤ 2.9V.

Reset asserts when under the reset condition of a button press or VDD ≤ 2.93V.

Reset Asserting Timing

Reset output needs to assert when the reset conditions are met for 60ms, and needs to de-assert after 60ms of no reset conditions.

Reset output asserts when the reset conditions are met for 62ms and deasserts after 62ms of no reset conditions.

Output Current

The output current must not exceed 500µA.

The output current is 300µA under the reset condition.
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