The sense delay corresponds to the configuration of CTS and the reset delay corresponds to the configuration of CTR. The sense and reset time delay can be set to a minimum value of 50µs and 80µs by leaving the CTS and CTR pins floating respectively, or a maximum value of approximately 6.5 seconds by connecting 10µF delay capacitor.

The relationship between external capacitor (C_{CT_EXT}) in Farads at CTS or CTR pins and the time delay in seconds is given by Equation 1.

Equation 1 is simplified to Equation 2 and Equation 3 by plugging R_CT and t_{D (CTS or CTR = OPEN)} given in
Section 5.5 and Section 5.6 section:

Equation 4 and Equation 5 solves for both external capacitor values (C_{CTS_EXT}) and (C_{CTR_EXT}) in units of Farads where t_D-SENSE and t_D are in units of seconds

The sense or reset delay varies according to three variables: the external capacitor (C_{CT_EXT}), CTS and CTR pin internal resistance (R_CT) provided in the Electrical Characteristics table, and a constant. The minimum and maximum variance due to the constant is show in Equation 6 and Equation 7 .

The recommended maximum sense and reset delay capacitors for the TPS3899 is limited to 10µF as this makes sure there is enough time for either capacitors to fully discharge when a voltage fault occurs. When a voltage fault occurs, the previously charged up capacitor discharges and if the monitored voltage returns from the fault condition before either delay capacitors discharges completely, both delays can be shorter than expected. The capacitors can begin charging from a voltage above zero and resulting in shorter than expected time delays. Larger delay capacitors can be used so long as the capacitors have enough time to fully discharge during the duration of the voltage fault. To make sure the capacitors are fully discharged, the time period or duration of the voltage fault needs to be greater than 10% of the programmed reset time delay.

Figure 6-2 shows the charge and discharge behavior on CTS and CTR that defines the sense and reset delays respectively. When SENSE transitions below V_IT-, the capacitor connected to CTS begins to charge. Once the CTS capacitor charges to an internal threshold shown as V_{TH_CTS}, RESET transitions to active-low logic state and the CTS capacitor then begins to discharge immediately. When SENSE transitions above V_IT- + V_HYS, the capacitor connected to CTR begins to charge. Once the CTR capacitor charges to the internal threshold V_{TH_CTR}, RESET releases back to inactive logic high state and the CTR capacitor begins to discharge immediately. Please note that for active-high variants, RESET follows the inverse behavior of RESET.

Figure 6-3 shows the charge and discharge behavior on CTS and CTR where the monitored voltage is VDD. Similar to Figure 6-2, Figure 6-3 illustrates a SENSE signal that is transitioning below V_IT- before the CTR capacitor reaches to an internal threshold voltage V_{TH_CTR} and t < t_D. The result of the CTR capacitor not reaching the internal threshold voltage V_{TH_CTR} is RESET becomes deasserted. Once RESET is deasserted, charging beings for the CTS capacitor. When the CTS voltage reaches the internal threshold V_{TH_CTS}, RESET becomes asserted. This phenomenon is caused by the SENSE falling edge triggering the discharging of the CTR capacitor and producing a deassert signal on the RESET output.