ZHCSKS5C September 2020 – January 2024 TPS3899
PRODUCTION DATA
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Device Comparison
- Pin Configuration and Functions
- 5 Specifications
- 6 Detailed Description
- 7 Application and Implementation
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
7.2.2 Detailed Design Procedure
The TPS3899DL01 can monitor any voltage above 0.505V using an external voltage divider. This device has a negative going input threshold voltage of 0.505V; however, the design needs to assert a reset when VDD drops below 2.9V. By using a resistor divider (R1 = 47.5kΩ, R2 = 10kΩ) the negative going threshold voltage becomes 2.93V. The device's positive going voltage threshold is VIT- + VHYS. The typical VHYS is 25.5mV. This in combination with the resistor divider makes the design's positive going threshold voltage equal to 3.08V. If VDD falls below 2.93V for the duration of sense delay (tD-SENSE), the reset asserts. If VDD rises above 3.08V for the duration of reset delay (tD), the reset deasserts. See Figure 7-2 for a timing diagram detailing the voltage levels and reset assertion/deassertion conditions.
Figure 7-2 Design 1 Timing DiagramThis design also enters a reset condition when the push-button (PB) is asserted. The push-button is tied to ground and when pressed drops the SENSE voltage to 0V, making the device assert a reset. As a good analog practice, a 0.1µF capacitor was also placed on VDD.
The desired reset timing conditions are sense delay time of 60ms (the time to trigger a
reset) and a reset delay time of 60ms (the time to recover from a reset). Using Equation 4 and Equation 5, respectively, to solve for CTS and CTR capacitor values, CTS = 0.1µF and CTR = 0.1µF.
These capacitor values give a nominal sense delay time of 62ms and nominal reset delay time
of 62ms. Figure 7-3 and
Figure 7-4 are the results of the described application where the measured sense and reset delay
time are shown respectively.
For the requirement of a maximum output current, an external pull-up resistor needs to be selected so that the current through the external pull-up resistor exceeds no more than 500µA. When the reset output is low, the voltage drop across the external pull-up resistor is equal to VDD. Ohm’s law is used to calculate the minimum resistor value. The resistor needs to be greater than 6kΩ to pull less than 500µA in the reset asserted low condition. A resistor value of 10kΩ was selected to accomplish this.
Note that this design does not account for tolerances.