SNVSBM4D March   2022  – October 2024 TPS389006-Q1 , TPS389R0-Q1

PRODMIX  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I2C
      2. 7.3.2  Auto Mask (AMSK)
      3. 7.3.3  Packet Error Checking (PEC)
      4. 7.3.4  VDD
      5. 7.3.5  MON
      6. 7.3.6  NIRQ
      7. 7.3.7  ADC
      8. 7.3.8  Time Stamp
      9. 7.3.9  NRST
      10. 7.3.10 Register Protection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Built-In Self Test and Configuration Load
        1. 7.4.1.1 Notes on BIST Execution
      2. 7.4.2 TPS389006/08-Q1,TPS389R0-Q1 Power ON
      3. 7.4.3 General Monitoring
        1. 7.4.3.1 IDLE Monitoring
        2. 7.4.3.2 ACTIVE Monitoring
        3. 7.4.3.3 Sequence Monitoring 1
          1. 7.4.3.3.1 ACT Transitions 0→1
          2. 7.4.3.3.2 SLEEP Transition 1→0
          3. 7.4.3.3.3 SLEEP Transition 0→1
        4. 7.4.3.4 Sequence Monitoring 2
          1. 7.4.3.4.1 ACT Transition 1→0
    5. 7.5 Register Maps
      1. 7.5.1 BANK0 Registers
      2. 7.5.2 BANK1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Multichannel Sequencer and Monitor
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Guidelines
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature
    2. 9.2 Documentation Support
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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7.5.1 BANK0 Registers

Table 7-9 lists the memory-mapped registers for the BANK0 registers. All register offset addresses not listed in Table 7-9 should be considered as reserved locations and the register contents should not be modified.

Table 7-9 BANK0 Registers
AddressAcronymBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
0x10INT_SRCF_OTHERRESERVEDTESTCONTROLMONITOR
0x11INT_MONITORSEQ_ONSEQ_OFFSEQ_EXSSEQ_ENSOV_LFOV_HFUV_LFUV_HF
0x12INT_UVHFUVHF[N]
0x14INT_UVLFUVLF[N]
0x16INT_OVHFOVHF[N]
0x18INT_OVLFOVLF[N]
0x1AINT_SEQ_ONF_SEQ_ON[N]
0x1CINT_SEQ_OFFF_SEQ_OFF[N]
0x1EINT_SEQ_EXSF_SEQ_EXS[N]
0x20INT_SEQ_ENSF_SEQ_ENS[N]
0x22INT_CONTROLRESERVEDF_CRCF_NIRQF_TSDF_SYNCF_PEC
0x23INT_TESTRESERVEDECC_SECECC_DEDI_BIST_CBIST
0x24INT_VENDORSelf-Test_CRCLDO_OV_ErrorNRST_mismatchFreq_DEV_ErrorSHORT_DETOPEN_DETRESERVED
0x30VMON_STATFAILSAFEST_BIDT_CST_VDDST_NIRQST_ACTSLPST_ACTSHDNST_SYNCRESERVED
0x31TEST_INFORESERVEDECC_SECECC_DEDBIST_VMBIST_NVMBIST_LBIST_A
0x32OFF_STATVIN[N]
0x34SEQ_REC_STATREC_ACTIVESEQTS_RDYSEQ_ON_RDYSEQ_OFF_RDYSEQ_EXS_RDYSEQ_ENS_RDY
0x35SEQ_OW_STATRSVDTS_OWSEQ_ON_OWSEQ_OFF_OWSEQ_EXS_OWSEQ_ENS_OW
0x36SEQ_ORD_STATSYNC_COUNT[7:0]
0x40MON_LVL[1]ADC[7:0]
0x41MON_LVL[2]ADC[7:0]
0x42MON_LVL[3]ADC[7:0]
0x43MON_LVL[4]ADC[7:0]
0x44MON_LVL[5]ADC[7:0]
0x45MON_LVL[6]ADC[7:0]
0x46MON_LVL[7]ADC[7:0]
0x47MON_LVL[8]ADC[7:0]
0x50SEQ_ON_LOG[1]ORDER[7:0]
0x51SEQ_ON_LOG[2]ORDER[7:0]
0x52SEQ_ON_LOG[3]ORDER[7:0]
0x53SEQ_ON_LOG[4]ORDER[7:0]
0x54SEQ_ON_LOG[5]ORDER[7:0]
0x55SEQ_ON_LOG[6]ORDER[7:0]
0x56SEQ_ON_LOG[7]ORDER[7:0]
0x57SEQ_ON_LOG[8]ORDER[7:0]
0x60SEQ_OFF_LOG[1]ORDER[7:0]
0x61SEQ_OFF_LOG[2]ORDER[7:0]
0x62SEQ_OFF_LOG[3]ORDER[7:0]
0x63SEQ_OFF_LOG[4]ORDER[7:0]
0x64SEQ_OFF_LOG[5]ORDER[7:0]
0x65SEQ_OFF_LOG[6]ORDER[7:0]
0x66SEQ_OFF_LOG[7]ORDER[7:0]
0x67SEQ_OFF_LOG[8]ORDER[7:0]
0x70SEQ_EXS_LOG[1]ORDER[7:0]
0x71SEQ_EXS_LOG[2]ORDER[7:0]
0x72SEQ_EXS_LOG[3]ORDER[7:0]
0x73SEQ_EXS_LOG[4]ORDER[7:0]
0x74SEQ_EXS_LOG[5]ORDER[7:0]
0x75SEQ_EXS_LOG[6]ORDER[7:0]
0x76SEQ_EXS_LOG[7]ORDER[7:0]
0x77SEQ_EXS_LOG[8]ORDER[7:0]
0x80SEQ_ENS_LOG[1]ORDER[7:0]
0x81SEQ_ENS_LOG[2]ORDER[7:0]
0x82SEQ_ENS_LOG[3]ORDER[7:0]
0x83SEQ_ENS_LOG[4]ORDER[7:0]
0x84SEQ_ENS_LOG[5]ORDER[7:0]
0x85SEQ_ENS_LOG[6]ORDER[7:0]
0x86SEQ_ENS_LOG[7]ORDER[7:0]
0x87SEQ_ENS_LOG[8]ORDER[7:0]
0x90SEQ_TIME_MSB[1]CLOCK[7:0]
0x91SEQ_TIME_LSB[1]CLOCK[7:0]
0x92SEQ_TIME_MSB[2]CLOCK[7:0]
0x93SEQ_TIME_LSB[2]CLOCK[7:0]
0x94SEQ_TIME_MSB[3]CLOCK[7:0]
0x95SEQ_TIME_LSB[3]CLOCK[7:0]
0x96SEQ_TIME_MSB[4]CLOCK[7:0]
0x97SEQ_TIME_LSB[4]CLOCK[7:0]
0x98SEQ_TIME_MSB[5]CLOCK[7:0]
0x99SEQ_TIME_LSB[5]CLOCK[7:0]
0x9ASEQ_TIME_MSB[6]CLOCK[7:0]
0x9BSEQ_TIME_LSB[6]CLOCK[7:0]
0x9CSEQ_TIME_MSB[7]CLOCK[7:0]
0x9DSEQ_TIME_LSB[7]CLOCK[7:0]
0x9ESEQ_TIME_MSB[8]CLOCK[7:0]
0x9FSEQ_TIME_LSB[8]CLOCK[7:0]
0xF0BANK_SELRESERVEDBANK SELECTION
0xF1PROT1RESERVEDWRKCWRKSCFGIENMONSEQ
0xF2PROT2RESERVEDWRKCWRKSCFGIENMONSEQ
0xF3PROT_MON2RESERVEDMON[N]
0xF9I2CADDRRESERVEDADDR_NVM[3:0]ADDR_STRAP[2:0]
0xFADEV_CFGRESERVEDSOC_IF

Complex bit access types are encoded to fit into small table cells. Table 7-10 shows the codes that are used for access types in this section.

Table 7-10 BANK0 Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
Write Type
WWWrite
W1CW
1C		Write
1 to clear
Reset or Default Value
-nValue after reset or the default value

7.5.1.1 INT_SRC Register (Address = 0x10) [Reset = 0xX0]

INT_SRC is shown in Table 7-11.

Return to the Summary Table.

Global Interrupt Source Status register. This register contains fault interrupts on UV/OV HF/LF interrupts and internal fault interrupt and other interrupt. INT_SRC represents the reason why NIRQ was asserted. When the host processor receives NIRQ, the processor can read this register to quickly determine the source of the interrupt. If this register is clear, then the device did not assert NIRQ.

Table 7-11 INT_SRC Register Field Descriptions
BitFieldTypeResetDescription
7F_OTHERR0b Vendor specific internal fault.
Details reported in INT_F_OTHER.
This bit represents the ORed value of all bits in INT_F_OTHER.
0b = No fault reported in INT_F_OTHER

1b = Fault reported in INT_F_OTHER
6:3RESERVEDRb Reserved
2TESTRxb Internal test or configuration load fault.
Details reported in INT_TEST.
Represents ORed value of all bits in INT_TEST.
0b = No test/configuration fault detected

1b = Test/configuration fault detected
1CONTROLRxb Control status or communication fault.
Details reported in INT_CONTROL.
Represents ORed value of all bits in INT_CONTROL.
0b = No status or communication fault detected

1b = Status or communication fault detected
0MONITORRxb Voltage or sequence monitor fault.
Details reported in INT_MONITOR.
Represents ORed value of all bits in INT_MONITOR.
0b = No voltage or sequence fault detected

1b = Voltage or sequence fault detected

7.5.1.2 INT_MONITOR Register (Address = 0x11) [Reset = 0xX0]

INT_MONITOR is shown in Table 7-12.

Return to the Summary Table.

Voltage and Sequence Monitor Interrupt Status register. This register contains fault interrupts for sequence entry/exit from act/sleep modes and HF and LF faults.

Table 7-12 INT_MONITOR Register Field Descriptions
BitFieldTypeResetDescription
7SEQ_ONR0b Power ON Sequence Fault.
Details reported in INT_SEQ_ON.
Represents ORed value of all bits in INT_SEQ_ON.
A Power ON Sequence fault occurs when the content of SEQ_ON_LOG[N] register does not match the value defined in SEQ_ON_EXP[N] register.
0b = No Power ON Sequence fault detected

1b = Power ON Sequence fault detected
6SEQ_OFFR0b Power OFF Sequence Fault.
Details reported in INT_SEQ_OFF.
Represents ORed value of all bits in INT_SEQ_OFF.
A Power OFF Sequence fault occurs when the content of SEQ_OFF_LOG[N] register does not match the value defined in SEQ_OFF_EXP[N] register.
0b = No Power OFF Sequence fault detected

1b = Power OFF Sequence fault detected
5SEQ_EXSR0b Exit Sleep Sequence Fault.
Details reported in INT_SEQ_EXS.
Represents ORed value of all bits in INT_SEQ_EXS.
An Exit Sleep Sequence fault occurs when the content of SEQ_EXS_LOG[N] register does not match the value defined in SEQ_EXS_EXP[N] register.
0b = No Exit Sleep Sequence fault detected

1b = Exit Sleep Sequence fault detected
4SEQ_ENSR0b Entry Sleep Sequence Fault.
Details reported in INT_SEQ_ENS.
Represents ORed value of all bits in INT_SEQ_ENS.
An Entry Sleep Sequence fault occurs when the content of SEQ_ENS_LOG[N] register does not match the value defined in SEQ_ENS_EXP[N] register.
0b = No Entry Sleep Sequence fault detected

1b = Entry Sleep Sequence fault detected
3OV_LFRxb Overvoltage Low Frequency Fault.
Details reported in INT_OVLF.
Represents ORed value of all bits in INT_OVLF.
0b = No OVLF fault detected

1b = OVLF fault detected
2OV_HFRxb Overvoltage High Frequency Fault.
Details reported in INT_OVHF.
Represents ORed value of all bits in INT_OVHF.
0b = No OVHF fault detected

1b = OVHF fault detected
1UV_LFRxb Undervoltage Low Frequency Fault.
Details reported in INT_UVLF.
Represents ORed value of all bits in INT_UVLF.
0b = No UVLF fault detected

1b = UVLF fault detected
0UV_HFRxb Undervoltage High Frequency Fault.
Details reported in INT_UVHF.
Represents ORed value of all bits in INT_UVHF.
0b = No UVHF fault detected

1b = UVHF fault detected

7.5.1.3 INT_UVHF Register (Address = 0x12) [Reset = 0xX0]

INT_UVHF is shown in Table 7-13.

Return to the Summary Table.

High Frequency channel Undervoltage Interrupt Status register. This register contains informtation on which channel had a UV HF fault.

Table 7-13 INT_UVHF Register Field Descriptions
BitFieldTypeResetDescription
7:0UVHF[N]R/W1Cxxxxb Undervoltage High Frequency Fault for channel N (1 through 8).
Trips if channel N High Frequency signal goes below UV_HF[N].
The recovery of the fault condition does NOT clear the bit.
The fault can only be cleared by the host with a write-1-to-clear.
Write-1-to-clear clears the bit only if the UVHF fault condition is also removed (channel N High Frequency signal is above UV_HF[N]).
0b = Channel N has no UVHF fault detected (or interrupt disabled in IEN_UVHF register)

1b = Channel N has UVHF fault detected

7.5.1.4 INT_UVLF Register (Address = 0x14) [Reset = 0xX0]

INT_UVLF is shown in Table 7-14.

Return to the Summary Table.

Low Frequency channel Undervoltage Interrupt Status register. This register contains informtation on which channel had a UV LF fault.

Table 7-14 INT_UVLF Register Field Descriptions
BitFieldTypeResetDescription
7:0UVLF[N]R/W1Cxxxxb Undervoltage Low Frequency Fault for channel N (1 through 8).
Trips if channel N Low Frequency signal goes below UV_LF[N].
The recovery of the fault condition does NOT clear the bit.
The fault can only be cleared by the host with a write-1-to-clear.
Write-1-to-clear clears the bit only if the UVLF fault condition is also removed (channel N Low Frequency signal is above UV_LF[N]).
0b = Channel N has no UVLF fault detected (or interrupt disabled in IEN_UVLF register)

1b = Channel N has UVLF fault detected

7.5.1.5 INT_OVHF Register (Address = 0x16) [Reset = 0xX0]

INT_OVHF is shown in Table 7-15.

Return to the Summary Table.

High Frequency channel Overvoltage Interrupt Status register. This register contains informtation on which channel had an OV HF fault.

Table 7-15 INT_OVHF Register Field Descriptions
BitFieldTypeResetDescription
7:0OVHF[N]R/W1Cxxxxb Overvoltage High Frequency Fault for channel N (1 through 8).
Trips if channel N High Frequency signal goes above OV_HF[N].
The recovery of the fault condition does NOT clear the bit.The faultcan only be cleared by the host with a write-1-to-clear.
Write-1-to-clear clears the bit only if the OVHF fault condition is also removed (channel N High Frequency signal is below OV_HF[N]).
0b = Channel N has noOVHF fault detected (or interrupt disabled in IEN_OVHF register)

1b = Channel N has OVHF fault detected

7.5.1.6 INT_OVLF Register (Address = 0x18) [Reset = 0xX0]

INT_OVLF is shown in Table 7-16.

Return to the Summary Table.

Low Frequency channel Overvoltage Interrupt Status register. This register contains informtation on which channel had an OV LF fault.

Table 7-16 INT_OVLF Register Field Descriptions
BitFieldTypeResetDescription
7:0OVLF[N]R/W1Cxxxxb Overvoltage Low Frequency Fault for channel N (1 through 8).
Trips if channel N Low Frequency signal goes above OV_LF[N].
The recovery of the fault condition does NOT clear the bit.The fault only be cleared by the host with a write-1-to-clear.
Write-1-to-clear clears the bit only if the OVLF fault condition is also removed (channel N Low Frequency signal is below OV_LF[N]).
0b = Channel N has no OVLF fault detected (or interrupt disabled in IEN_OVLF register)

1b = Channel N has OVLF fault detected

7.5.1.7 INT_SEQ_ON Register (Address = 0x1A) [Reset = 0xX0]

INT_SEQ_ON is shown in Table 7-17.

Return to the Summary Table.

Power ON Sequence (ACT/ SLEEP 0 to 1) Interrupt Status register. This register contains informtation on which channel did not follow on sequence.

Table 7-17 INT_SEQ_ON Register Field Descriptions
BitFieldTypeResetDescription
7:0F_SEQ_ON[N]R/W1Cxxxxb Power ON Sequence Fault for channel N (1 through 8).
Trips if channel N recorded Power ON Sequence counter in SEQ_ON_LOG[N] register does not match the value defined in SEQ_ON_EXP[N] register.
The recovery of the fault condition does NOT clear the bit.The fault only be cleared by the host with a write-1-to-clear.
Write-1-to-clear clears the bit.
The bit sets again during next sequence if the same fault is detected.
0b = Channel N has no Power ON Sequence fault detected (or interrupt disabled in IEN_SEQ_ON register)

1b = Channel N has Power ON Sequence fault detected

7.5.1.8 INT_SEQ_OFF Register (Address = 0x1C) [Reset = 0xX0]

INT_SEQ_OFF is shown in Table 7-18.

Return to the Summary Table.

Power OFF Sequence (ACT/ SLEEP 1 to 0) Interrupt Status register. This register contains informtation on which channel did not follow off sequence.

Table 7-18 INT_SEQ_OFF Register Field Descriptions
BitFieldTypeResetDescription
7:0F_SEQ_OFF[N]R/W1Cxxxxb Power OFF Sequence Fault for channel N (1 through 8).
Trips if channel N recorded Power OFF Sequence counter in SEQ_OFF_LOG[N] register does not match the value defined in SEQ_OFF_EXP[N] register.
The recovery of the fault condition does NOT clear the bit.The fault only be cleared by the host with a write-1-to-clear.
Write-1-to-clear clears the bit.
The bit sets again during next sequence if the same fault is detected.
0b = Channel N has no Power OFF Sequence fault detected (or interrupt disabled in IEN_SEQ_OFF register)

1b = Channel N has Power OFF Sequence fault detected

7.5.1.9 INT_SEQ_EXS Register (Address = 0x1E) [Reset = 0xX0]

INT_SEQ_EXS is shown in Table 7-19.

Return to the Summary Table.

Exit Sleep Sequence (ACT/ SLEEP 0 to 1) Interrupt Status register. This register contains informtation on which channel did not follow sleep exit sequence.

Table 7-19 INT_SEQ_EXS Register Field Descriptions
BitFieldTypeResetDescription
7:0F_SEQ_EXS[N]R/W1Cxxxxb Exit Sleep Sequence Fault for channel N (1 through 8).
Trips if channel N recorded Exit Sleep Sequence counter in SEQ_EXS_LOG[N] register does not match the value defined in SEQ_EXS_EXP[N] register.
The recovery of the fault condition does NOT clear the bit.The fault only be cleared by the host with a write-1-to-clear.
Write-1-to-clear clears the bit.
The bit sets again during next sequence if the same fault is detected.
0b = Channel N has no Exit Sleep Sequence fault detected (or interrupt disabled in IEN_SEQ_EXS register)

1b = Channel N has Exit Sleep Sequence fault detected

7.5.1.10 INT_SEQ_ENS Register (Address = 0x20) [Reset = 0xX0]

INT_SEQ_ENS is shown in Table 7-20.

Return to the Summary Table.

Entry Sleep Sequence (SLEEP 1 to 0) Interrupt Status register. This register contains informtation on which channel did not follow sleep entry sequence.

Table 7-20 INT_SEQ_ENS Register Field Descriptions
BitFieldTypeResetDescription
7:0F_SEQ_ENS[N]R/W1Cxxxxb Entry Sleep Sequence Fault for channel N (1 through 8).
Trips if channel N recorded Entry Sleep Sequence counter in SEQ_ENS_LOG[N] register does not match the value defined in SEQ_ENS_EXP[N] register.
0b = Channel N has no Entry Sleep Sequence fault detected (or interrupt disabled in IEN_SEQ_ENS register)

1b = Channel N has Entry Sleep Sequence fault detected

7.5.1.11 INT_CONTROL Register (Address = 0x22) [Reset = 0xX0]

INT_CONTROL is shown in Table 7-21.

Return to the Summary Table.

Control and Communication Interrupt Status Register.

Table 7-21 INT_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
7:5RESERVEDRb Reserved
4F_CRCR/W1C0b Runtime register CRC Fault: The recovery of the fault condition does NOT clear the bit.The fault only be cleared by the host with a write-1-to-clear.
Write-1-to-clear clears the bit.
The bit sets again during next register CRC check if the same fault is detected.
0b = No fault detected (or IEN_CONTROL.RT_CRC is disabled)

1b = Register CRC fault detected
3F_NIRQR/W1Cxb Interrupt pin fault (fault bit always enabled
no enable bit available): The recovery of the fault condition does NOT clear the bit.The fault only be cleared by the host with a write-1-to-clear.
Write-1-to-clear clears the bit only if the NIRQ fault condition is also removed.
0b = No fault detected on NIRQ pin

1b = Low resistance path to supply detected on NIRQ pin
2F_TSDR/W1Cxb Thermal Shutdown fault: The recovery of the fault condition does NOT clear the bit.The fault only be cleared by the host with a write-1-to-clear.
Write-1-to-clear clears the bit only if the TSD fault condition is also removed.
0b = No TSD fault detected (or IEN_CONTROL.TSD is disabled)

1b = TSD fault detected
1F_SYNCR/W1Cxb SYNC pin fault: The recovery of the fault condition does NOT clear the bit.The fault only be cleared by the host with a write-1-to-clear.
Write-1-to-clear clears the bit only if the SYNC fault condition is also removed.
0b = No fault detected on SYNC pin (or IEN_CONTROL.SYNC is disabled)

1b = Low resistance path to supply detected on SYNC pin
0F_PECR/W1Cxb Packet Error Checking fault: The recovery of the fault condition does NOT clear the bit.The fault only be cleared by the host with a write-1-to-clear.
Write-1-to-clear clears the bit.
The bit will be set again during next I2C transaction if the same fault is detected.

7.5.1.12 INT_TEST Register (Address = 0x23) [Reset = 0xX0]

INT_TEST is shown in Table 7-22.

Return to the Summary Table.

Internal Test and Configuration Load Interrupt Status Register.

Table 7-22 INT_TEST Register Field Descriptions
BitFieldTypeResetDescription
7:4RESERVEDRb Reserved
3ECC_SECR/W1Cxb ECC single-error corrected on OTP configuration load: Write-1-to-clear clears the bit.
The bit will be set again during next OTP configuration load if the same fault is detected.
0b = No single-error corrected (or IEN_TEST.ECC_SEC is disabled)

1b = Single-error corrected
2ECC_DEDR/W1Cxb ECC double-error detected on OTP configuration load: The fault bit is always enabled (there is no associated interrupt enable bit).
Write-1-to-clear clears the bit.
The bit will be set again during next OTP configuration load if the same fault is detected.
0b = No double-error detected on OTP load

1b = Double-error detected on OTP load
1I_BIST_CR/W1Cxb Indication of Built-In Self-Test complete: Write-1-to-clear clears the bit.
The bit sets again on completion of next BIST execution.Write-1-to-clear clears the bit.
The bit sets again on completion of next BIST execution.
0b = BIST not complete (or IEN_TEST.BIST_C is disabled)

1b = BIST complete
0BISTR/W1Cxb Built-In Self-Test fault: Write-1-to-clear clears the bit.
The bit sets again during next BIST execution if the same fault is detected.
0b = No BIST fault detected (or IEN_TEST.BIST is disabled)

1b = BIST fault detected

7.5.1.13 INT_VENDOR Register (Address = 0x24) [Reset = 0xX0]

INT_VENDOR is shown in Table 7-23.

Return to the Summary Table.

This register contains various internal faults and ADDR detect pin fault.

Table 7-23 INT_VENDOR Register Field Descriptions
BitFieldTypeResetDescription
7Self-Test_CRCR/W1C0b Startup register CRC

0b
0= Self-test Pass

0b
1 = Self-test Fail
Write-
1-to clear
6LDO_OV_ErrorR/W1C0b Internal LDO fault:

0 = No internal LDO fault detected

1 = Internal LDO fault detected Write-
1-to-clear clears the bit.
5NRST_mismatchR/W1C0b NRST PIN drive state and read back state error
1b = Mismatch fault detected The recovery of the fault condition does NOT clear the bit.The fault can only be cleared by the host with a write-1-to-clear. Write-1-to-clear clears the bit only if the NRST fault condition is also removed.
4Freq_DEV_ErrorR/W1C0b Internal Oscillator fault:

0 = No internal oscillator fault detected

1 = Internal oscillator fault detected Write-
1-to-clear clears the bit.
3SHORT_DETR/W1Cxb Address Pin fault:

0 = No address pin fault detected

1 = Address pin fault detected Write-
1-to-clear clears the bit.
2OPEN_DETR/W1Cxb Address Pin fault:

0 = No address pin fault detected

1 = Address pin fault detected Write-
1-to-clear clears the bit.
1:0RESERVEDRb Reserved

7.5.1.14 VMON_STAT Register (Address = 0x30) [Reset = 0xX0]

VMON_STAT is shown in Table 7-24.

Return to the Summary Table.

Status flags for internal operations and other non critical conditions. Status register showing completion of BIST, whether active or sleep or active/shutdown.

Table 7-24 VMON_STAT Register Field Descriptions
BitFieldTypeResetDescription
7FAILSAFER0b Fail Safe state:

0 = Not in Fail Safe state

1 = In Fail Safe state
6ST_BIDT_CR0b Built-In Self-Test state:

0 = BIST not complete

1 = BIST complete
5ST_VDDR0b Current state of VDD pin:

0 = VDD pin is low.


1 = VDD pin is high.
4ST_NIRQR0b Current state of NIRQ input:

0 = NIRQ pin driven low by system.


1 = NIRQ pin driven high by system.
3ST_ACTSLPRxb Current state of SLEEP input:

0 = SLEEP pin driven low by system.


1 = SLEEP pin driven high by system.
2ST_ACTSHDNRxb Current state of ACT input:

0 = ACT pin driven low by system.


1 = ACT pin driven high by system.
1ST_SYNCRxb Current state of SYNC pin:

0 = SYNC pin is low.


1 = SYNC pin is high.
0RESERVEDRb Reserved

7.5.1.15 TEST_INFO Register (Address = 0x31) [Reset = 0xX0]

TEST_INFO is shown in Table 7-25.

Return to the Summary Table.

Internal Self-Test and ECC information.

Table 7-25 TEST_INFO Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDRb Reserved
5ECC_SECR0b Status of ECC single-error correction on OTP configuration load.


0 = no error correction applied

1 = single-error correction applied
4ECC_DEDR0b Status of ECC double-error detection on OTP configuration load.


0 = no double-error detected

1 = double-error detected
3BIST_VMRxb Status of Volatile Memory test output from BIST.


0 = Volatile Memory test pass

1 = Volatile Memory test fail
2BIST_NVMRxb Status of Non-Volatile Memory test output from BIST.


0 = Non-Volatile Memory test pass

1 = Non-Volatile Memory test fail
1BIST_LRxb Status of Logic test output from BIST.


0 = Logic test pass

1 = Logic test fail
0BIST_ARxb Status of Analog test output from BIST.


0 = Analog test pass

1 = Analog test fail

7.5.1.16 OFF_STAT Register (Address = 0x32) [Reset = 0xX0]

OFF_STAT is shown in Table 7-26.

Return to the Summary Table.

Channel OFF status.

Table 7-26 OFF_STAT Register Field Descriptions
BitFieldTypeResetDescription
7:0VIN[N]Rxxxxb This register represents the OFF status of each channel:

0 = channel N is NOT OFF

1 = channel N is OFF (below OFF threshold)

7.5.1.17 SEQ_REC_STAT Register (Address = 0x34) [Reset = 0xX0]

SEQ_REC_STAT is shown in Table 7-27.

Return to the Summary Table.

Sequence recording status register.

Table 7-27 SEQ_REC_STAT Register Field Descriptions
BitFieldTypeResetDescription
7REC_ACTIVER0b Indicates the status of sequence logging (recording):

0 = No sequence recording active.


1 = ACT or SLEEP or SEQ_REC_CTL.REC_START initiated a power sequence and recording is active.
6:5SEQR0b Current sequence being recorded: 00b = Power ON (ACT 01)
01b = Power OFF (ACT 10)
10b = Sleep Exit (SLEEP 01)
11b = Sleep Entry (SLEEP 10)
4TS_RDYR0b Timestamp data availability in SEQ_TIME_xSB registers: If EN_TS_OW=
0 this bit is cleared when TS_ACK is written to
1 by the host.
If EN_TS_OW=
1 this bit is cleared when all the SEQ_TIME_xSB[N] registers for the enabled channels (in VIN_CH_EN register) are read.
If the bit is set and REC_ACTIVE is also set, then the data in SEQ_TIME_xSB registers is being overwritten.


0 = No new data available or data already read.


1 = New data available (data still needs to be read).
3SEQ_ON_RDYRxb Power ON sequence data availability in SEQ_ON_LOG registers: If EN_SEQ_OW=
0 this bit is cleared when SEQ_ON_ACK is written to
1 by the host.
If EN_SEQ_OW=
1 this bit is cleared when all the SEQ_ON_LOG registers for the enabled channels (in VIN_CH_EN register) are read.
If the bit is set and REC_ACTIVE is set and SEQ[
1:
0]=
00b, then the data in SEQ_ON_LOG registers is being overwritten.


0 = No new data available or data already read.


1 = New data available (data still needs to be read).
2SEQ_OFF_RDYRxb Power OFF sequence data availability in SEQ_OFF_LOG registers: If EN_SEQ_OW=
0 this bit is cleared when SEQ_OFF_ACK is written to
1 by the host.
If EN_SEQ_OW=
1 this bit is cleared when all the SEQ_OFF_LOG registers for the enabled channels (in VIN_CH_EN register) are read.
If the bit is set and REC_ACTIVE is set and SEQ[
1:
0]=
01b, then the data in SEQ_OFF_LOG registers is being overwritten.


0 = No new data available or data already read.


1 = New data available (data still needs to be read).
1SEQ_EXS_RDYRxb Sleep Exit sequence data availability in SEQ_EXS_LOG registers: If EN_SEQ_OW=
0 this bit is cleared when SEQ_EXS_ACK is written to
1 by the host.
If EN_SEQ_OW=
1 this bit is cleared when all the SEQ_EXS_LOG registers for the enabled channels (in VIN_CH_EN register) are read.
If the bit is set and REC_ACTIVE is set and SEQ[
1:
0]=
10b, then the data in SEQ_EXS_LOG registers is being overwritten.


0 = No new data available or data already read.


1 = New data available (data still needs to be read).
0SEQ_ENS_RDYRxb Sleep Entry sequence data availability in SEQ_ENS_LOG registers: If EN_SEQ_OW=
0 this bit is cleared when SEQ_ENS_ACK is written to
1 by the host.
If EN_SEQ_OW=
1 this bit is cleared when all the SEQ_ENS_LOG registers for the enabled channels (in VIN_CH_EN register) are read.
If the bit is set and REC_ACTIVE is set and SEQ[
1:
0]=
11b, then the data in SEQ_ENS_LOG registers is being overwritten.


0 = No new data available or data already read.


1 = New data available (data still needs to be read).

7.5.1.18 SEQ_OW_STAT Register (Address = 0x35) [Reset = 0xX0]

SEQ_OW_STAT is shown in Table 7-28.

Return to the Summary Table.

Sequence recording overwrite status register.

Table 7-28 SEQ_OW_STAT Register Field Descriptions
BitFieldTypeResetDescription
7:5RSVDR0b RSVD
4TS_OWR0b Timestamp data overwritten status:

0 = No data was overwritten

1 = Data was overwritten (if VMON_MISC.EN_TS_OW=
1), or data can not be written (if VMON_MISC.EN_TS_OW=
0)
3SEQ_ON_OWRxb Power ON sequence data overwritten status:

0 = No data was overwritten

1 = Data was overwritten (if VMON_MISC.EN_SEQ_OW=
1), or data can not be written (if VMON_MISC.EN_SEQ_OW=
0)
2SEQ_OFF_OWRxb Power OFF sequence data overwritten status:
0 = No data was overwritten
1 = Data was overwritten (if VMON_MISC.EN_SEQ_OW=
1), or data can not be written (if VMON_MISC.EN_SEQ_OW=
0)
1SEQ_EXS_OWRxb Sleep Exit sequence data overwritten status:

0 = No data was overwritten

1 = Data was overwritten (if VMON_MISC.EN_SEQ_OW=
1), or data can not be written (if VMON_MISC.EN_SEQ_OW=
0)
0SEQ_ENS_OWRxb Sleep Entry sequence data overwritten status:

0 = No data was overwritten

1 = Data was overwritten (if VMON_MISC.EN_SEQ_OW=
1), or data can not be written (if VMON_MISC.EN_SEQ_OW=
0)

7.5.1.19 SEQ_ORD_STAT Register (Address = 0x36) [Reset = 0xX0]

SEQ_ORD_STAT is shown in Table 7-29.

Return to the Summary Table.

Sequencing/SYNC counter (rail order) register value.

Table 7-29 SEQ_ORD_STAT Register Field Descriptions
BitFieldTypeResetDescription
7:0SYNC_COUNT[7:0]Rxxxxb This register represents the counter value during a power/sleep sequence.
It corresponds to the number of SYNC falling edges detected, and used as tag value for monitored channels.

7.5.1.20 MON_LVL[1] Register (Address = 0x40) [Reset = 0xX0]

MON_LVL[1] is shown in Table 7-30.

Return to the Summary Table.

For ADC readout -of each channel - 8bits

Table 7-30 MON_LVL[1] Register Field Descriptions
BitFieldTypeResetDescription
7:0ADC[7:0]Rxxxxb This register represents the 8-bit voltage level of channel 1.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling set to 1x, the 8-bit value represents the range 0.2V to 1.475V with 1LSB=5mV.
With scaling set to 4x, the 8-bit value represents the range 0.8V to 5.9V with 1LSB=20mV.

7.5.1.21 MON_LVL[2] Register (Address = 0x41) [Reset = 0xX0]

MON_LVL[2] is shown in Table 7-31.

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For ADC readout -of each channel - 8bits

Table 7-31 MON_LVL[2] Register Field Descriptions
BitFieldTypeResetDescription
7:0ADC[7:0]Rxxxxb This register represents the 8-bit voltage level of channel 2.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling set to 1x, the 8-bit value represents the range 0.2V to 1.475V with 1LSB=5mV.
With scaling set to 4x, the 8-bit value represents the range 0.8V to 5.9V with 1LSB=20mV.

7.5.1.22 MON_LVL[3] Register (Address = 0x42) [Reset = 0xX0]

MON_LVL[3] is shown in Table 7-32.

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For ADC readout -of each channel - 8bits

Table 7-32 MON_LVL[3] Register Field Descriptions
BitFieldTypeResetDescription
7:0ADC[7:0]Rxxxxb This register represents the 8-bit voltage level of channel 3.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling set to 1x, the 8-bit value represents the range 0.2V to 1.475V with 1LSB=5mV.
With scaling set to 4x, the 8-bit value represents the range 0.8V to 5.9V with 1LSB=20mV.

7.5.1.23 MON_LVL[4] Register (Address = 0x43) [Reset = 0xX0]

MON_LVL[4] is shown in Table 7-33.

Return to the Summary Table.

For ADC readout -of each channel - 8bits

Table 7-33 MON_LVL[4] Register Field Descriptions
BitFieldTypeResetDescription
7:0ADC[7:0]Rxxxxb This register represents the 8-bit voltage level of channel 4.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling set to 1x, the 8-bit value represents the range 0.2V to 1.475V with 1LSB=5mV.
With scaling set to 4x, the 8-bit value represents the range 0.8V to 5.9V with 1LSB=20mV.

7.5.1.24 MON_LVL[5] Register (Address = 0x44) [Reset = 0xX0]

MON_LVL[5] is shown in Table 7-34.

Return to the Summary Table.

For ADC readout -of each channel - 8bits

Table 7-34 MON_LVL[5] Register Field Descriptions
BitFieldTypeResetDescription
7:0ADC[7:0]Rxxxxb This register represents the 8-bit voltage level of channel 5.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling set to 1x, the 8-bit value represents the range 0.2V to 1.475V with 1LSB=5mV.
With scaling set to 4x, the 8-bit value represents the range 0.8V to 5.9V with 1LSB=20mV.

7.5.1.25 MON_LVL[6] Register (Address = 0x45) [Reset = 0xX0]

MON_LVL[6] is shown in Table 7-35.

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For ADC readout -of each channel - 8bits

Table 7-35 MON_LVL[6] Register Field Descriptions
BitFieldTypeResetDescription
7:0ADC[7:0]Rxxxxb This register represents the 8-bit voltage level of channel 6.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling set to 1x, the 8-bit value represents the range 0.2V to 1.475V with 1LSB=5mV.
With scaling set to 4x, the 8-bit value represents the range 0.8V to 5.9V with 1LSB=20mV.

7.5.1.26 MON_LVL[7] Register (Address = 0x46) [Reset = 0xX0]

MON_LVL[7] is shown in Table 7-36.

Return to the Summary Table.

For ADC readout -of each channel - 8bits

Table 7-36 MON_LVL[7] Register Field Descriptions
BitFieldTypeResetDescription
7:0ADC[7:0]Rxxxxb This register represents the 8-bit voltage level of channel 5.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling set to 1x, the 8-bit value represents the range 0.2V to 1.475V with 1LSB=5mV.
With scaling set to 4x, the 8-bit value represents the range 0.8V to 5.9V with 1LSB=20mV.

7.5.1.27 MON_LVL[8] Register (Address = 0x47) [Reset = 0xX0]

MON_LVL[8] is shown in Table 7-37.

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For ADC readout -of each channel - 8bits

Table 7-37 MON_LVL[8] Register Field Descriptions
BitFieldTypeResetDescription
7:0ADC[7:0]Rxxxxb This register represents the 8-bit voltage level of channel 6.
The 8-bit value interpretation depends on the scaling setting in register VRANGE_MULT.
With scaling set to 1x, the 8-bit value represents the range 0.2V to 1.475V with 1LSB=5mV.
With scaling set to 4x, the 8-bit value represents the range 0.8V to 5.9V with 1LSB=20mV.

7.5.1.28 SEQ_ON_LOG[1] Register (Address = 0x50) [Reset = 0xX0]

SEQ_ON_LOG[1] is shown in Table 7-38.

Return to the Summary Table.

Channel N Power ON sequence order value (ACT/ SLEEP 0 to 1).

Table 7-38 SEQ_ON_LOG[1] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Power ON sequence order value for channel 1.
The sequence order value is the tag assigned to the channel during the sequence triggered by ACT.
The tag is assigned when the voltage rising level passes the UV_LF[N] threshold.
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.29 SEQ_ON_LOG[2] Register (Address = 0x51) [Reset = 0xX0]

SEQ_ON_LOG[2] is shown in Table 7-39.

Return to the Summary Table.

Channel N Power ON sequence order value (ACT/ SLEEP 0 to 1).

Table 7-39 SEQ_ON_LOG[2] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Power ON sequence order value for channel 2.
The sequence order value is the tag assigned to the channel during the sequence triggered by ACT.
The tag is assigned when the voltage rising level passes the UV_LF[N] threshold.
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.30 SEQ_ON_LOG[3] Register (Address = 0x52) [Reset = 0xX0]

SEQ_ON_LOG[3] is shown in Table 7-40.

Return to the Summary Table.

Channel N Power ON sequence order value (ACT/ SLEEP 0 to 1).

Table 7-40 SEQ_ON_LOG[3] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Power ON sequence order value for channel 3.
The sequence order value is the tag assigned to the channel during the sequence triggered by ACT.
The tag is assigned when the voltage rising level passes the UV_LF[N] threshold.
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.31 SEQ_ON_LOG[4] Register (Address = 0x53) [Reset = 0xX0]

SEQ_ON_LOG[4] is shown in Table 7-41.

Return to the Summary Table.

Channel N Power ON sequence order value (ACT/ SLEEP 0 to 1).

Table 7-41 SEQ_ON_LOG[4] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Power ON sequence order value for channel 4.
The sequence order value is the tag assigned to the channel during the sequence triggered by ACT.
The tag is assigned when the voltage rising level passes the UV_LF[N] threshold.
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.32 SEQ_ON_LOG[5] Register (Address = 0x54) [Reset = 0xX0]

SEQ_ON_LOG[5] is shown in Table 7-42.

Return to the Summary Table.

Channel N Power ON sequence order value (ACT/ SLEEP 0 to 1).

Table 7-42 SEQ_ON_LOG[5] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Power ON sequence order value for channel 5.
The sequence order value is the tag assigned to the channel during the sequence triggered by ACT.
The tag is assigned when the voltage rising level passes the UV_LF[N] threshold.
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.33 SEQ_ON_LOG[6] Register (Address = 0x55) [Reset = 0xX0]

SEQ_ON_LOG[6] is shown in Table 7-43.

Return to the Summary Table.

Channel N Power ON sequence order value (ACT/ SLEEP 0 to 1).

Table 7-43 SEQ_ON_LOG[6] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Power ON sequence order value for channel 6.
The sequence order value is the tag assigned to the channel during the sequence triggered by ACT.
The tag is assigned when the voltage rising level passes the UV_LF[N] threshold.
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.34 SEQ_ON_LOG[7] Register (Address = 0x56) [Reset = 0xX0]

SEQ_ON_LOG[7] is shown in Table 7-44.

Return to the Summary Table.

Channel N Power ON sequence order value (ACT/ SLEEP 0 to 1).

Table 7-44 SEQ_ON_LOG[7] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Power ON sequence order value for channel 7.
The sequence order value is the tag assigned to the channel during the sequence triggered by ACT.
The tag is assigned when the voltage rising level passes the UV_LF[N] threshold.
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.35 SEQ_ON_LOG[8] Register (Address = 0x57) [Reset = 0xX0]

SEQ_ON_LOG[8] is shown in Table 7-45.

Return to the Summary Table.

Channel N Power ON sequence order value (ACT/ SLEEP 0 to 1).

Table 7-45 SEQ_ON_LOG[8] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Power ON sequence order value for channel 8.
The sequence order value is the tag assigned to the channel during the sequence triggered by ACT.
The tag is assigned when the voltage rising level passes the UV_LF[N] threshold.
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.36 SEQ_OFF_LOG[1] Register (Address = 0x60) [Reset = 0xX0]

SEQ_OFF_LOG[1] is shown in Table 7-46.

Return to the Summary Table.

Channel N Power OFF sequence order value (ACT 1 to 0).

Table 7-46 SEQ_OFF_LOG[1] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Power OFF sequence order value for channel 1.
The sequence order value is the tag assigned to the channel during the sequence triggered by ACT.
The tag is assigned when the voltage falling level passes the OFF threshold (200mV).
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.37 SEQ_OFF_LOG[2] Register (Address = 0x61) [Reset = 0xX0]

SEQ_OFF_LOG[2] is shown in Table 7-47.

Return to the Summary Table.

Channel N Power OFF sequence order value (ACT 1 to 0).

Table 7-47 SEQ_OFF_LOG[2] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Power OFF sequence order value for channel 2.
The sequence order value is the tag assigned to the channel during the sequence triggered by ACT.
The tag is assigned when the voltage falling level passes the OFF threshold (200mV).
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.38 SEQ_OFF_LOG[3] Register (Address = 0x62) [Reset = 0xX0]

SEQ_OFF_LOG[3] is shown in Table 7-48.

Return to the Summary Table.

Channel N Power OFF sequence order value (ACT 1 to 0).

Table 7-48 SEQ_OFF_LOG[3] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Power OFF sequence order value for channel 3.
The sequence order value is the tag assigned to the channel during the sequence triggered by ACT.
The tag is assigned when the voltage falling level passes the OFF threshold (200mV).
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.39 SEQ_OFF_LOG[4] Register (Address = 0x63) [Reset = 0xX0]

SEQ_OFF_LOG[4] is shown in Table 7-49.

Return to the Summary Table.

Channel N Power OFF sequence order value (ACT 1 to 0).

Table 7-49 SEQ_OFF_LOG[4] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Power OFF sequence order value for channel 4.
The sequence order value is the tag assigned to the channel during the sequence triggered by ACT.
The tag is assigned when the voltage falling level passes the OFF threshold (200mV).
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.40 SEQ_OFF_LOG[5] Register (Address = 0x64) [Reset = 0xX0]

SEQ_OFF_LOG[5] is shown in Table 7-50.

Return to the Summary Table.

Channel N Power OFF sequence order value (ACT 1 to 0).

Table 7-50 SEQ_OFF_LOG[5] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Power OFF sequence order value for channel 5.
The sequence order value is the tag assigned to the channel during the sequence triggered by ACT.
The tag is assigned when the voltage falling level passes the OFF threshold (200mV).
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.41 SEQ_OFF_LOG[6] Register (Address = 0x65) [Reset = 0xX0]

SEQ_OFF_LOG[6] is shown in Table 7-51.

Return to the Summary Table.

Channel N Power OFF sequence order value (ACT 1 to 0).

Table 7-51 SEQ_OFF_LOG[6] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Power OFF sequence order value for channel 6.
The sequence order value is the tag assigned to the channel during the sequence triggered by ACT.
The tag is assigned when the voltage falling level passes the OFF threshold (200mV).
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.42 SEQ_OFF_LOG[7] Register (Address = 0x66) [Reset = 0xX0]

SEQ_OFF_LOG[7] is shown in Table 7-52.

Return to the Summary Table.

Channel N Power OFF sequence order value (ACT 1 to 0).

Table 7-52 SEQ_OFF_LOG[7] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Power OFF sequence order value for channel 7.
The sequence order value is the tag assigned to the channel during the sequence triggered by ACT.
The tag is assigned when the voltage falling level passes the OFF threshold (200mV).
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.43 SEQ_OFF_LOG[8] Register (Address = 0x67) [Reset = 0xX0]

SEQ_OFF_LOG[8] is shown in Table 7-53.

Return to the Summary Table.

Channel N Power OFF sequence order value (ACT 1 to 0).

Table 7-53 SEQ_OFF_LOG[8] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Power OFF sequence order value for channel 8.
The sequence order value is the tag assigned to the channel during the sequence triggered by ACT.
The tag is assigned when the voltage falling level passes the OFF threshold (200mV).
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.44 SEQ_EXS_LOG[1] Register (Address = 0x70) [Reset = 0xX0]

SEQ_EXS_LOG[1] is shown in Table 7-54.

Return to the Summary Table.

Channel N Sleep Exit sequence order value (SLEEP 0 to 1).

Table 7-54 SEQ_EXS_LOG[1] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Sleep Exit sequence order value for channel 1.
The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP.
The tag is assigned when the voltage rising level passes the UV_LF[1] threshold.
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.45 SEQ_EXS_LOG[2] Register (Address = 0x71) [Reset = 0xX0]

SEQ_EXS_LOG[2] is shown in Table 7-55.

Return to the Summary Table.

Channel N Sleep Exit sequence order value (SLEEP 0 to 1).

Table 7-55 SEQ_EXS_LOG[2] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Sleep Exit sequence order value for channel 2.
The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP.
The tag is assigned when the voltage rising level passes the UV_LF[2] threshold.
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.46 SEQ_EXS_LOG[3] Register (Address = 0x72) [Reset = 0xX0]

SEQ_EXS_LOG[3] is shown in Table 7-56.

Return to the Summary Table.

Channel N Sleep Exit sequence order value (SLEEP 0 to 1).

Table 7-56 SEQ_EXS_LOG[3] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Sleep Exit sequence order value for channel 3.
The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP.
The tag is assigned when the voltage rising level passes the UV_LF[3] threshold.
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.47 SEQ_EXS_LOG[4] Register (Address = 0x73) [Reset = 0xX0]

SEQ_EXS_LOG[4] is shown in Table 7-57.

Return to the Summary Table.

Channel N Sleep Exit sequence order value (SLEEP 0 to 1).

Table 7-57 SEQ_EXS_LOG[4] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Sleep Exit sequence order value for channel 4.
The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP.
The tag is assigned when the voltage rising level passes the UV_LF[4] threshold.
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.48 SEQ_EXS_LOG[5] Register (Address = 0x74) [Reset = 0xX0]

SEQ_EXS_LOG[5] is shown in Table 7-58.

Return to the Summary Table.

Channel N Sleep Exit sequence order value (SLEEP 0 to 1).

Table 7-58 SEQ_EXS_LOG[5] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Sleep Exit sequence order value for channel 5.
The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP.
The tag is assigned when the voltage rising level passes the UV_LF[5] threshold.
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.49 SEQ_EXS_LOG[6] Register (Address = 0x75) [Reset = 0xX0]

SEQ_EXS_LOG[6] is shown in Table 7-59.

Return to the Summary Table.

Channel N Sleep Exit sequence order value (SLEEP 0 to 1).

Table 7-59 SEQ_EXS_LOG[6] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Sleep Exit sequence order value for channel 6.
The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP.
The tag is assigned when the voltage rising level passes the UV_LF[6] threshold.
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.50 SEQ_EXS_LOG[7] Register (Address = 0x76) [Reset = 0xX0]

SEQ_EXS_LOG[7] is shown in Table 7-60.

Return to the Summary Table.

Channel N Sleep Exit sequence order value (SLEEP 0 to 1).

Table 7-60 SEQ_EXS_LOG[7] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Sleep Exit sequence order value for channel 7.
The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP.
The tag is assigned when the voltage rising level passes the UV_LF[5] threshold.
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.51 SEQ_EXS_LOG[8] Register (Address = 0x77) [Reset = 0xX0]

SEQ_EXS_LOG[8] is shown in Table 7-61.

Return to the Summary Table.

Channel N Sleep Exit sequence order value (SLEEP 0 to 1).

Table 7-61 SEQ_EXS_LOG[8] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Sleep Exit sequence order value for channel 8.
The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP.
The tag is assigned when the voltage rising level passes the UV_LF[6] threshold.
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.52 SEQ_ENS_LOG[1] Register (Address = 0x80) [Reset = 0xX0]

SEQ_ENS_LOG[1] is shown in Table 7-62.

Return to the Summary Table.

Channel N Sleep Entry sequence order value (SLEEP 1 to 0).

Table 7-62 SEQ_ENS_LOG[1] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Sleep Entry sequence order value for channel 1.
The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP.
The tag is assigned when the voltage falling level passes the OFF threshold (200mV).
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.53 SEQ_ENS_LOG[2] Register (Address = 0x81) [Reset = 0xX0]

SEQ_ENS_LOG[2] is shown in Table 7-63.

Return to the Summary Table.

Channel N Sleep Entry sequence order value (SLEEP 1 to 0).

Table 7-63 SEQ_ENS_LOG[2] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Sleep Entry sequence order value for channel 2.
The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP.
The tag is assigned when the voltage falling level passes the OFF threshold (200mV).
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.54 SEQ_ENS_LOG[3] Register (Address = 0x82) [Reset = 0xX0]

SEQ_ENS_LOG[3] is shown in Table 7-64.

Return to the Summary Table.

Channel N Sleep Entry sequence order value (SLEEP 1 to 0).

Table 7-64 SEQ_ENS_LOG[3] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Sleep Entry sequence order value for channel 3.
The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP.
The tag is assigned when the voltage falling level passes the OFF threshold (200mV).
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.55 SEQ_ENS_LOG[4] Register (Address = 0x83) [Reset = 0xX0]

SEQ_ENS_LOG[4] is shown in Table 7-65.

Return to the Summary Table.

Channel N Sleep Entry sequence order value (SLEEP 1 to 0).

Table 7-65 SEQ_ENS_LOG[4] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Sleep Entry sequence order value for channel 4.
The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP.
The tag is assigned when the voltage falling level passes the OFF threshold (200mV).
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.56 SEQ_ENS_LOG[5] Register (Address = 0x84) [Reset = 0xX0]

SEQ_ENS_LOG[5] is shown in Table 7-66.

Return to the Summary Table.

Channel N Sleep Entry sequence order value (SLEEP 1 to 0).

Table 7-66 SEQ_ENS_LOG[5] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Sleep Entry sequence order value for channel 5.
The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP.
The tag is assigned when the voltage falling level passes the OFF threshold (200mV).
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.57 SEQ_ENS_LOG[6] Register (Address = 0x85) [Reset = 0xX0]

SEQ_ENS_LOG[6] is shown in Table 7-67.

Return to the Summary Table.

Channel N Sleep Entry sequence order value (SLEEP 1 to 0).

Table 7-67 SEQ_ENS_LOG[6] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Sleep Entry sequence order value for channel 6.
The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP.
The tag is assigned when the voltage falling level passes the OFF threshold (200mV).
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.58 SEQ_ENS_LOG[7] Register (Address = 0x86) [Reset = 0xX0]

SEQ_ENS_LOG[7] is shown in Table 7-68.

Return to the Summary Table.

Channel N Sleep Entry sequence order value (SLEEP 1 to 0).

Table 7-68 SEQ_ENS_LOG[7] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Sleep Entry sequence order value for channel 7.
The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP.
The tag is assigned when the voltage falling level passes the OFF threshold (200mV).
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.59 SEQ_ENS_LOG[8] Register (Address = 0x87) [Reset = 0xX0]

SEQ_ENS_LOG[8] is shown in Table 7-69.

Return to the Summary Table.

Channel N Sleep Entry sequence order value (SLEEP 1 to 0).

Table 7-69 SEQ_ENS_LOG[8] Register Field Descriptions
BitFieldTypeResetDescription
7:0ORDER[7:0]Rxxxxb This register stores the Sleep Entry sequence order value for channel 8.
The sequence order value is the tag assigned to the channel during the sequence triggered by SLEEP.
The tag is assigned when the voltage falling level passes the OFF threshold (200mV).
The tag value is the SYNC_ORD_COUNT at the time the threshold is passed.

7.5.1.60 SEQ_TIME_MSB[1] Register (Address = 0x90) [Reset = 0xX0]

SEQ_TIME_MSB[1] is shown in Table 7-70.

Return to the Summary Table.

Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-70 SEQ_TIME_MSB[1] Register Field Descriptions
BitFieldTypeResetDescription
7:0CLOCK[7:0]Rxxxxb This register stores the MSB of the sequence timestamp for channel 1.
The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP.
The timestamp is stored when the voltage rising level passes the UV_LF[1] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01).
The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10).
The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

7.5.1.61 SEQ_TIME_LSB[1] Register (Address = 0x91) [Reset = 0xX0]

SEQ_TIME_LSB[1] is shown in Table 7-71.

Return to the Summary Table.

Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-71 SEQ_TIME_LSB[1] Register Field Descriptions
BitFieldTypeResetDescription
7:0CLOCK[7:0]Rxxxxb This register stores the LSB of the sequence timestamp for channel 1.
The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP.
The timestamp is stored when the voltage rising level passes the UV_LF[1] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01).
The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10).
The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

7.5.1.62 SEQ_TIME_MSB[2] Register (Address = 0x92) [Reset = 0xX0]

SEQ_TIME_MSB[2] is shown in Table 7-72.

Return to the Summary Table.

Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-72 SEQ_TIME_MSB[2] Register Field Descriptions
BitFieldTypeResetDescription
7:0CLOCK[7:0]Rxxxxb This register stores the MSB of the sequence timestamp for channel 2.
The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP.
The timestamp is stored when the voltage rising level passes the UV_LF[2] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01).
The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10).
The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

7.5.1.63 SEQ_TIME_LSB[2] Register (Address = 0x93) [Reset = 0xX0]

SEQ_TIME_LSB[2] is shown in Table 7-73.

Return to the Summary Table.

Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-73 SEQ_TIME_LSB[2] Register Field Descriptions
BitFieldTypeResetDescription
7:0CLOCK[7:0]Rxxxxb This register stores the LSB of the sequence timestamp for channel 2.
The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP.
The timestamp is stored when the voltage rising level passes the UV_LF[2] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01).
The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10).
The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

7.5.1.64 SEQ_TIME_MSB[3] Register (Address = 0x94) [Reset = 0xX0]

SEQ_TIME_MSB[3] is shown in Table 7-74.

Return to the Summary Table.

Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-74 SEQ_TIME_MSB[3] Register Field Descriptions
BitFieldTypeResetDescription
7:0CLOCK[7:0]Rxxxxb This register stores the MSB of the sequence timestamp for channel 3.
The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP.
The timestamp is stored when the voltage rising level passes the UV_LF[3] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01).
The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10).
The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

7.5.1.65 SEQ_TIME_LSB[3] Register (Address = 0x95) [Reset = 0xX0]

SEQ_TIME_LSB[3] is shown in Table 7-75.

Return to the Summary Table.

Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-75 SEQ_TIME_LSB[3] Register Field Descriptions
BitFieldTypeResetDescription
7:0CLOCK[7:0]Rxxxxb This register stores the LSB of the sequence timestamp for channel 3.
The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP.
The timestamp is stored when the voltage rising level passes the UV_LF[3] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01).
The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10).
The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

7.5.1.66 SEQ_TIME_MSB[4] Register (Address = 0x96) [Reset = 0xX0]

SEQ_TIME_MSB[4] is shown in Table 7-76.

Return to the Summary Table.

Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-76 SEQ_TIME_MSB[4] Register Field Descriptions
BitFieldTypeResetDescription
7:0CLOCK[7:0]Rxxxxb This register stores the MSB of the sequence timestamp for channel 4.
The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP.
The timestamp is stored when the voltage rising level passes the UV_LF[4] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01).
The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10).
The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

7.5.1.67 SEQ_TIME_LSB[4] Register (Address = 0x97) [Reset = 0xX0]

SEQ_TIME_LSB[4] is shown in Table 7-77.

Return to the Summary Table.

Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-77 SEQ_TIME_LSB[4] Register Field Descriptions
BitFieldTypeResetDescription
7:0CLOCK[7:0]Rxxxxb This register stores the LSB of the sequence timestamp for channel 4.
The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP.
The timestamp is stored when the voltage rising level passes the UV_LF[4] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01).
The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power 200mVd Sleep Entry sequences (ACT 10 or SLEEP 10).
The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

7.5.1.68 SEQ_TIME_MSB[5] Register (Address = 0x98) [Reset = 0xX0]

SEQ_TIME_MSB[5] is shown in Table 7-78.

Return to the Summary Table.

Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-78 SEQ_TIME_MSB[5] Register Field Descriptions
BitFieldTypeResetDescription
7:0CLOCK[7:0]Rxxxxb This register stores the MSB of the sequence timestamp for channel 5.
The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP.
The timestamp is stored when the voltage rising level passes the UV_LF[5] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01).
The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10).
The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

7.5.1.69 SEQ_TIME_LSB[5] Register (Address = 0x99) [Reset = 0xX0]

SEQ_TIME_LSB[5] is shown in Table 7-79.

Return to the Summary Table.

Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-79 SEQ_TIME_LSB[5] Register Field Descriptions
BitFieldTypeResetDescription
7:0CLOCK[7:0]Rxxxxb This register stores the LSB of the sequence timestamp for channel 5.
The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP.
The timestamp is stored when the voltage rising level passes the UV_LF[5] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01).
The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10).
The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

7.5.1.70 SEQ_TIME_MSB[6] Register (Address = 0x9A) [Reset = 0xX0]

SEQ_TIME_MSB[6] is shown in Table 7-80.

Return to the Summary Table.

Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-80 SEQ_TIME_MSB[6] Register Field Descriptions
BitFieldTypeResetDescription
7:0CLOCK[7:0]Rxxxxb This register stores the MSB of the sequence timestamp for channel 6.
The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP.
The timestamp is stored when the voltage rising level passes the UV_LF[6] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01).
The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10).
The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

7.5.1.71 SEQ_TIME_LSB[6] Register (Address = 0x9B) [Reset = 0xX0]

SEQ_TIME_LSB[6] is shown in Table 7-81.

Return to the Summary Table.

Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-81 SEQ_TIME_LSB[6] Register Field Descriptions
BitFieldTypeResetDescription
7:0CLOCK[7:0]Rxxxxb This register stores the LSB of the sequence timestamp for channel 6.
The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP.
The timestamp is stored when the voltage rising level passes the UV_LF[6] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01).
The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10).
The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

7.5.1.72 SEQ_TIME_MSB[7] Register (Address = 0x9C) [Reset = 0xX0]

SEQ_TIME_MSB[7] is shown in Table 7-82.

Return to the Summary Table.

Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-82 SEQ_TIME_MSB[7] Register Field Descriptions
BitFieldTypeResetDescription
7:0CLOCK[7:0]Rxxxxb This register stores the MSB of the sequence timestamp for channel 7.
The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP.
The timestamp is stored when the voltage rising level passes the UV_LF[7] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01).
The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10).
The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

7.5.1.73 SEQ_TIME_LSB[7] Register (Address = 0x9D) [Reset = 0xX0]

SEQ_TIME_LSB[7] is shown in Table 7-83.

Return to the Summary Table.

Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-83 SEQ_TIME_LSB[7] Register Field Descriptions
BitFieldTypeResetDescription
7:0CLOCK[7:0]Rxxxxb This register stores the LSB of the sequence timestamp for channel 7.
The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP.
The timestamp is stored when the voltage rising level passes the UV_LF[7] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01).
The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10).
The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

7.5.1.74 SEQ_TIME_MSB[8] Register (Address = 0x9E) [Reset = 0xX0]

SEQ_TIME_MSB[8] is shown in Table 7-84.

Return to the Summary Table.

Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-84 SEQ_TIME_MSB[8] Register Field Descriptions
BitFieldTypeResetDescription
7:0CLOCK[7:0]Rxxxxb This register stores the MSB of the sequence timestamp for channel 8.
The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP.
The timestamp is stored when the voltage rising level passes the UV_LF[8] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01).
The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10).
The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

7.5.1.75 SEQ_TIME_LSB[8] Register (Address = 0x9F) [Reset = 0xX0]

SEQ_TIME_LSB[8] is shown in Table 7-85.

Return to the Summary Table.

Channel N Sequence timestamp value MSB and LSB (all sequences).

Table 7-85 SEQ_TIME_LSB[8] Register Field Descriptions
BitFieldTypeResetDescription
7:0CLOCK[7:0]Rxxxxb This register stores the LSB of the sequence timestamp for channel 8.
The sequence timer value is the time assigned to the channel during the sequence triggered by ACT or SLEEP.
The timestamp is stored when the voltage rising level passes the UV_LF[8] threshold for Power ON and Sleep Exit sequences (ACT 01 or SLEEP 01).
The timestamp is stored when the voltage falling level passes the OFF threshold (200mV) for Power OFF and Sleep Entry sequences (ACT 10 or SLEEP 10).
The least significant bit corresponds to 50µs (equal to tSEQ_LSB).

7.5.1.76 BANK_SEL Register (Address = 0xF0) [Reset = 0x00]

BANK_SEL is shown in Table 7-86.

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Bank select=0 for Bank 0 and 1 for Bank 1

Table 7-86 BANK_SEL Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDRb Reserved
0BANK SELECTIONR/Wb Register Bank selection number.

7.5.1.77 PROT1 Register (Address = 0xF1) [Reset = 0x00]

PROT1 is shown in Table 7-87.

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Protection selection registers. To write-protect a register group, the host must set the relevant bit in both registers. For security, registers PROT1 and PROT2 need to have POR value = 0x00 and become read-only once set until power cycle. Once set to 1, the bit cannot be cleared to 0 by the host. They can be cleared (and allow writing different VMON registers configurations) through: A power cycle A reset through VMON_CTL.RESET BIST executed on exiting Sequence 2 (if TEST_CFG.AT_SHDN=1).

Table 7-87 PROT1 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDRb Reserved
5WRKCR/Wb

0b
0 = Control Working (WRKC) registers are writeable.


0b
1 = Writes to control working registers are ignored.
4WRKSR/Wb

0b
0 = Sequence Working (WRKS) registers are writeable.


0b
1 = Writes to sequence working registers are ignored.
3CFGR/Wb

0b
0 = Configuration (CFG) registers are writeable.


0b
1 = Writes to configuration registers are ignored.
2IENR/Wb

0b
0 = Interrupt Enable (IEN) registers are writeable.


0b
1 = Writes to interrupt enable registers are ignored.
1MONR/Wb

0b
0 = Monitor (MON[N]) registers are writeable.


0b
1 = Writes to monitor registers selected in PROT_MON
1 register are ignored.
0SEQR/Wb

0b
0 = Sequence (SEQ) Registers are writeable.


0b
1 = Writes to sequence registers are ignored.

7.5.1.78 PROT2 Register (Address = 0xF2) [Reset = 0x00]

PROT2 is shown in Table 7-88.

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Protection selection registers. To write-protect a register group, the host must set the relevant bit in both registers. For security, registers PROT1 and PROT2 need to have POR value = 0x00 and become read-only once set until power cycle. Once set to 1, the bit cannot be cleared to 0 by the host. They can be cleared (and allow writing different VMON registers configurations) through: A power cycle A reset through VMON_CTL.RESET BIST executed on exiting Sequence 2 (if TEST_CFG.AT_SHDN=1).

Table 7-88 PROT2 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDRb Reserved
5WRKCR/Wb

0b
0 = Control Working (WRKC) registers are writeable.


0b
1 = Writes to control working registers are ignored.
4WRKSR/Wb

0b
0 = Sequence Working (WRKS) registers are writeable.


0b
1 = Writes to sequence working registers are ignored.
3CFGR/Wb

0b
0 = Configuration (CFG) registers are writeable.


0b
1 = Writes to configuration registers are ignored.
2IENR/Wb

0b
0 = Interrupt Enable (IEN) registers are writeable.


0b
1 = Writes to interrupt enable registers are ignored.
1MONR/Wb

0b
0 = Monitor (MON[N]) registers are writeable.


0b
1 = Writes to monitor registers selected in PROT_MON
1 register are ignored.
0SEQR/Wb

0b
0 = Sequence (SEQ) Registers are writeable.


0b
1 = Writes to sequence registers are ignored.

7.5.1.79 PROT_MON2 Register (Address = 0xF3) [Reset = 0xC1]

PROT_MON2 is shown in Table 7-89.

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Monitor channels configuration protection.

Table 7-89 PROT_MON2 Register Field Descriptions
BitFieldTypeResetDescription
7:6RESERVEDRb Reserved
5:0MON[N]R/W1b This register selects the monitor channels configurations that will be protected once PROT
1, PROT
2 registers are written to protect the MON group.


0 = Monitor configuration registers for channel N are writeable.


1 = Writes to monitor configuration registers for channel N are ignored.

7.5.1.80 I2CADDR Register (Address = 0xF9) [Reset = 0xX0]

I2CADDR is shown in Table 7-90.

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3 LSB bits are decided based on resistor value and 5 MSB bits are based on OTP NVM. ADDR_NVM has default value of 30 (Factory default setting)

Table 7-90 I2CADDR Register Field Descriptions
BitFieldTypeResetDescription
7RESERVEDRb Reserved
6:3ADDR_NVM[3:0]Rxb I2C address four most significant bits.
Set in NVM.
2:0ADDR_STRAP[2:0]Rxxxb I2C address three least significant bits.
Set by the strap level detected on ADDR pin, from 000b to 111b.

7.5.1.81 DEV_CFG Register (Address = 0xFA) [Reset = 0xX0]

DEV_CFG is shown in Table 7-91.

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Status of I2C interface voltage levels, 0 for 3.3V I/F and 1 for 1.2/1.8V interface (Factory default setting)

Table 7-91 DEV_CFG Register Field Descriptions
BitFieldTypeResetDescription
7:1RESERVEDRb Reserved
0SOC_IFRxb Host SoC Interface (includes I
2C, ACT, SLEEP, and SYNC).
0 =
3.
3V
1 =
1.
2V/
1.
8V
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