The TPS4005x uses a closed-loop soft-start system to ensure a controlled ramp of the output during start-up. The reference voltage used for the start-up is derived in the following manner. A capacitor (C_SS/SD) is connected to the SS/SD pin. There is a ramped voltage generated at this pin by charging C_SS/SD with a current source. A value of 0.85 V is subtracted from the voltage at the SS/SSD pin and is applied to a non-inverting input of the error amplifier. This is the effective soft-start ramp voltage, V_SSRMP. The error amplifier also has the 0.7-V reference (V_FB) voltage applied to a non-inverting input. The structure of the error amplifier input stage is such that the lower of V_FB or V_SSRMP becomes the dominant voltage that the error amplifier uses to regulate the FB pin. This provides a clean, closed-loop start-up while V_SSRMP is lower than V_FB and a precision reference regulated supply as V_SSRMP climbs above V_FB. To ensure a controlled ramp-up of the output voltage, the soft-start time must be greater than the L-C_O time constant as described in Equation 5.

Equation 5.

where

• t_START is the start-up ramp time in s.

There is a direct correlation between t_START and the input current required during start-up. The faster t_START, the higher the input current required during start-up. This relationship is described in more detail in the Programming the Current Limit section. The soft-start capacitance, C_SS/SD, is described in Equation 6.

For applications in which the V_IN supply ramps up slowly (typically between 50 ms and 100 ms), it can be necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO tripping. The soft-start time must be longer than the time that the V_IN supply transitions between 6 V and 7 V.

Equation 6.

where

• I_SS/SD is the soft-start charge current (typical value is 2.35 μA).
• V_FB is the feedback reference voltage (typical value is 0.7 V).