7.3.5 Shutdown and Sequencing

The TPS40077 can be shut down by pulling the SS pin below 250 mV. In this state, both of the output drivers are in the low-output state, turning off both of the power FETs. This places the output of the converter in a high-impedance state. When shutting down the converter, a crisp pulldown of the SS pin is preferred to a slow pulldown. A slow pulldown could allow the output to be pulled low, possibly sinking current from the load. As a general rule of thumb, the fall time of SS when shutting down the converter should be no more than 1/10th of the control loop crossover frequency. An example of a shutdown interface is shown in Figure 23.

Figure 23. TPS40077 Shutdown

In a similar manner, power supplies based on the TPS40077 can be sequenced by connecting the PGD pin of the first supply to come up to the SS pin of the second supply as shown in Figure 24.

Figure 24. TPS40077 Sequencing