9.1 Layout Guidelines

The TPS40077 provides separate signal ground (SGND) and power ground (PGND) pins. Take care to properly separation of the circuit grounds. Each ground must consist of a plane to minimize its impedance, if possible. The high-power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor (DBP), and the input capacitor should be connected to PGND plane.

Connect sensitive nodes such as the FB resistor divider and RT to the SGND plane. The SGND plane must only make a single-point connection to the PGND plane. TI recommends that the SGND pin be tied to the copper area for the thermal pad underneath the chip. Tie the PGND to the thermal-pad copper area as well, and make the connection to the power circuit ground from the PGND pin. Reference the output voltage divider to the SGND pin.

Component placement must ensure that bypass capacitors (LVPB and DBP) are located as close as possible to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not be located near high-dv/dt nodes such as HDRV, LDRV, BOOST, and the switch node (SW). Failure to follow careful layout practices results in suboptimal operation. More detailed information can be found in the TPS40077EVM user's guide (SLVU192).