Figure 7-5 illustrates an example layout. For the controller, it is important to connect carefully noise-sensitive signals such as RT, SS, FB, and COMP as close to the IC device as possible and connect to AGND as shown. The thermal pad must be connected to any internal PCB ground planes using multiple vias directly underneath the IC device. AGND and PGND must be connected at a single point.

High-performance FETs such as NexFET™ power MOSFETs from Texas Instruments, require careful attention to the layout. Minimize the distance between the positive node of the input ceramic capacitor and the drain pin of the control (high-side) FET. Minimize the distance between the negative node of the input ceramic capacitor and the source pin of the synchronize (low-side) FET. Because of the large gate drive, smaller gate charge, and faster turn-on times of the high-performance FETs, use a minimum of four 10-µF ceramic input capacitors such as TDK #C3216X5R1A106M. Ensure the layout allows a continuous flow of the power planes.

The layout of the HPA578 EVM is shown in Figure 7-5 through Figure 7-8 for reference.