The TRK pin is used for output voltage tracking. The output voltage is regulated so that the FB pin equals the lowest of the internal reference voltage (V_REF) or the level-shifted SS pin voltage (SS_EAMP) or the TRK pin voltage. Once the TRK pin goes above the reference voltage, then the output voltage is no longer governed by the TRK pin, but it is governed by the reference voltage.

If the voltage tracking function is used, then it must be noted that the SS pin capacitor must remain connected to SS pin and is also used for FAULT timing. For proper tracking using the TRK pin, the tracking voltage must be allowed to rise only after SS_EAMP has exceeded V_REF, so that there is no possibility of the TRK pin voltage being higher than the SS_EAMP voltage. From Figure 6-6, for SS_EAMP = 0.6 V, the SS pin voltage is typically 1.7 V.

The maximum slew rate on the TRK pin must be determined by the output capacitance and feedback loop bandwidth. A higher slew rate can possibly trip overcurrent protection.

Figure 6-9 shows the tracking functional block. For SS_EAMP voltages greater than TRK pin voltage, the V_OUT is given by Equation 12 and Equation 13.

For 0 V < V_TRK < V_REF

Equation 12.

For V_TRK > V_REF

Equation 13.

Figure 6-9 Tracking Functional Block

There are three potential applications for the tracking function.

• Simultaneous voltage tracking
• Ratiometric voltage tracking
• Sequential start-up mode

The tracking function configurations and waveforms are shown in Figure 6-10, Figure 6-11, Figure 6-12, Figure 6-13, Figure 6-14, and Figure 6-15 respectively.

In simultaneous voltage tracking, shown in Figure 6-10, tracking signals VTRK1 and VTRK2 of two modules, POL1 and POL2, start up at the same time, and their output voltages VOUT1initial and VOUT2initial are approximately the same during initial startup. Because VTRK1 and VTRK2 are less than V_REF (0.6 V, typical), Equation 12 is used. As a result, components selection must meet Equation 14.

Equation 14.

After the lower output voltage setting reaches the output-voltage V_OUT1 set point, where V_TRK1 increases above V_REF, the output voltage of the other one (V_OUT2) continues increasing until it reaches its own set point, where V_TRK2 increases above V_REF. At that time, Equation 13 is used. As a result, the resistor settings must meet Equation 15 and Equation 16.

Equation 15.

Equation 16.

Equation 14 can be simplified into Equation 17 by substituting terms from Equation 15 and Equation 16.

Equation 17.

If 5-V V_OUT2 and 2.5-V V_OUT1 are required, according to Equation 15, Equation 16, and Equation 17, the selected components can be as follows:

• R₅ = R₆ = R₄ = R₂ =10 kΩ
• R₁ = 3.16 kΩ
• R₃ = 1.37 kΩ

Figure 6-10 Simultaneous Voltage-Tracking Schematic

Figure 6-11 Simultaneous Voltage-Tracking Waveform

In ratiometric voltage tracking as shown in Figure 6-12, the two tracking voltages, VTRK1 and VTRK2, for two modules, POL1 and POL2, are the same. Their output voltages, VOUT1 and VOUT2, are different with different voltage dividers, R2–R1 and R4–R3. VOUT1 and VOUT2 increase proportionally and reach their output voltage set points at approximately the same time.

Figure 6-12 Ratiometric Voltage-Tracking Schematic

Figure 6-13 Ratiometric Voltage-Tracking Waveform

Sequential start-up is shown in Figure 6-14. During start-up of the first module, POL1, its PGOOD1 is pulled to low. Because PGOOD1 is connected to soft-start SS2 of the second module, POL2, is not able to charge its soft-start capacitor. After output voltage VOUT1 of POL1 reaches its setting point, PGOOD1 is released. POL2 starts charging its soft-start capacitor. Finally, output voltage V_OUT2 of POL2 reaches its setting point.

Figure 6-14 Sequential Start-Up Schematic

Figure 6-15 Sequential Start-Up Waveform