ZHCS826C January 2012 – November 2023 TPS40170-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| INPUT SUPPLY | ||||||
| VVIN | Input voltage range | 4.5 | 60 | V | ||
| ISD | Shutdown current | VENABLE < 100 mV | 1 | 2.5 | µA | |
| IQQ | Operating current, drivers not switching | VENABLE ≥ 2 V, fSW = 300 kHz | 4.5 | mA | ||
| ENABLE | ||||||
| VDIS | ENABLE pin voltage to disable the device | 100 | mV | |||
| VEN | ENABLE pin voltage to enable the device | 600 | mV | |||
| IENABLE | ENABLE pin source current | 300 | nA | |||
| 8-V AND 3.3-V REGULATORS | ||||||
| VVBP | 8-V regulator output voltage | VENABLE ≥ 2 V, 8.2 V < VVIN ≤ 60 V, 0 mA < IIN < 20 mA | 7.8 | 8.0 | 8.3 | V |
| VDO | 8-V regulator dropout voltage, VVIN-VVBP | 4.5 < VVIN ≤ 8.2 V, VEN ≥ 2 V, IIN = 10 mA | 110 | 200 | mV | |
| VVDD | 3.3-V regulator output voltage | VENABLE ≥ 2 V, 4.5 V < VVIN ≤ 60 V, 0 mA < IIN < 5 mA | 3.22 | 3.3 | 3.42 | V |
| FIXED AND PROGRAMMABLE UVLO | ||||||
| VUVLO | Programmable UVLO ON voltage (at UVLO pin) | VENABLE ≥ 2 V | 878 | 900 | 919 | mV |
| IUVLO | Hysteresis current out of UVLO pin | VENABLE ≥ 2 V , UVLO pin > VUVLO | 4.06 | 5 | 6.2 | µA |
| VBPON | VBP turnon voltage | VENABLE ≥ 2 V, UVLO pin > VUVLO | 3.85 | 4.4 | V | |
| VBPOFF | VBP turnoff voltage | 3.6 | 4.05 | |||
| VBPHYS | VBP UVLO Hysteresis voltage | 180 | 400 | mV | ||
| REFERENCE | ||||||
| VREF | Reference voltage (+ input of the error amplifier) | TJ = 25°C, 4.5 V < VVIN ≤ 60 V | 594 | 600 | 606 | mV |
| –40°C ≤ TJ ≤ 125°C, 4.5 V < VVIN ≤ 60 V | 591 | 600 | 609 | |||
| OSCILLATOR | ||||||
| fSW | Switching frequency | Range (typical) | 100 | 600 | kHz | |
| RRT = 100 kΩ, 4.5 V < VVIN ≤ 60 V | 90 | 100 | 110 | |||
| RRT = 31.6 kΩ, 4.5 V < VVIN ≤ 60 V | 270 | 300 | 330 | |||
| RRT = 14.3 kΩ, 4.5 V < VVIN ≤ 60 V | 540 | 600 | 660 | |||
| VVALLEY | Valley voltage | 0.7 | 1 | 1.2 | V | |
| KPWM(1) | PWM gain (VVIN / VRAMP) | 4.5 V < VVIN ≤ 60 V | 14 | 15 | 16 | V/V |
| PWM AND DUTY CYCLE | ||||||
| tON(min)(1) | Minimum controlled pulse | VVIN = 4.5 V, fSW = 300 kHz | 100 | 150 | ns | |
| VVIN = 12 V, fSW = 300 kHz | 75 | 100 | ||||
| VVIN = 60 V, fSW = 300 kHz | 50 | 80 | ||||
| tOFF(max)(1) | Minimum OFF time | VVIN = 12V, fSW = 300 kHz | 170 | 250 | ns | |
| DMAX(1) | Maximum duty cycle | fSW = 100 kHz, 4.5 V < VVIN ≤ 60 V | 95% | |||
| fSW = 300 kHz, 4.5 V < VVIN ≤ 60 V | 91% | |||||
| fSW = 600 kHz, 4.5 V < VVIN ≤ 60 V | 82% | |||||
| ERROR AMPLIFIER | ||||||
| GBWP(1) | Gain bandwidth product | 7 | 10 | 13 | MHz | |
| AOL(1) | Open-loop gain | 80 | 90 | 95 | dB | |
| IIB | Input bias current | 100 | nA | |||
| IEAOP | Output source current | VVFB = 0 V | 2 | mA | ||
| IEAOM | Output sink current | VVFB = 1 V | 2 | mA | ||
| PROGRAMMABLE SOFT START | ||||||
| ISS(source,start) | Soft-start source current | VSS < 0.5 V, VSS = 0.25 V | 42 | 52 | 62 | µA |
| ISS(source,normal) | Soft-start source current | VSS > 0.5 V, VSS = 1.5 V | 9.3 | 11.6 | 13.9 | µA |
| ISS(sink) | Soft-start sink current | VSS = 1.5 V | 0.77 | 1.05 | 1.33 | µA |
| VSS(fltH) | SS pin HIGH voltage during fault (OC or thermal) reset timing | 2.38 | 2.5 | 2.61 | V | |
| VSS(fltL) | SS pin LOW voltage during fault (OC or thermal) reset timing | 235 | 300 | 375 | mV | |
| VSS(steady_state) | SS pin voltage during steady-state | 3.25 | 3.3 | 3.5 | V | |
| VSS(offst) | Initial offset voltage from SS pin to error amplifier input | 525 | 650 | 775 | mV | |
| TRACKING | ||||||
| VTRK(ctrl)(1) | Range of TRK which overrides VREF | 4.5 V < VIN ≤ 60 V | 0 | 600 | mV | |
| SYNCHRONIZATION (PRIMARY/SECONDARY) | ||||||
| VMSTR | M/S pin voltage in primary mode | 3.9 | VIN | V | ||
| VSLV(0) | M/S pin voltage in secondary 0° mode | 1.25 | 1.75 | V | ||
| VSLV(180) | M/S pin voltage in secondary 180° mode | 0 | 0.75 | V | ||
| ISYNC(in) | SYNC pin pulldown current | M/S configured as secondary-
0° or secondary-180° | 8 | 11 | 14 | µA |
| VSYNC(in_high) | SYNC pin input high-voltage level | 2 | V | |||
| VSYNC(in_low) | SYNC pin input low-voltage level | 0.8 | V | |||
| tSYNC(high_min) | Minimum SYNC high pulse duration | 40 | 50 | ns | ||
| tSYNC(low_min) | Minimum SYNC low pulse duration | 40 | 50 | ns | ||
| GATE DRIVERS | ||||||
| RHDHI | High-side driver pullup resistance | CLOAD = 2.2 nF, IDRV = 300 mA, TA = –40°C to 125°C | 1.37 | 2.64 | 4 | Ω |
| RHDLO | High-side driver pulldown resistance | 1.08 | 2.4 | 4 | Ω | |
| RLDHI | Low-side driver pullup resistance | 1.37 | 2.4 | 4 | Ω | |
| RLDLO | Low-side driver pulldown resistance | 0.44 | 1.1 | 1.7 | Ω | |
| tNON-OVERLAP1 | Time delay between HDRV fall and LDRV rise | CLOAD = 2.2 nF, VHDRV = 2 V, VLDRV = 2 V | 50 | ns | ||
| tNON-OVERLAP2 | Time delay between HDRV rise and LDRV fall | 60 | ||||
| OVERCURRENT PROTECTION (LOW-SIDE MOSFET SENSING) | ||||||
| IILIM | ILIM pin source current | 4.5 V < VIN < 60 V, TA = 25°C | 9 | 9.75 | 10.45 | µA |
| 4.5 V < VIN < 60 V, TA = –40°C to 125°C | 7 | 12 | ||||
| IILIM,(ss) | ILIM pin source current during soft-start | 4.5 V < VIN < 60 V, TA = 25°C | 15 | µA | ||
| 4.5 V < VIN < 60 V, TA = –40°C to 125°C | 7 | 12 | ||||
| IILIM, Tc(1) | Temperature coefficient of ILIM current | 4.5 V < VIN < 60 V | 1400 | ppm | ||
| VILIM(1) | ILIM pin voltage operating range | 4.5 V < VIN < 60 V | 50 | 300 | mV | |
| OCPTH | Overcurrent protection threshold (voltage across low-side FET for detecting overcurrent) | RILIM = 10 kΩ, IILIM = 10 µA (VILIM = 100 mV) | –110 | –100 | –84 | mV |
| SHORT CIRCUIT PROTECTION HIGH-SIDE MOSFET SENSING) | ||||||
| VLDRV(max) | LDRV pin maximum voltage during calibration | RLDRV = open | 300 | 360 | mV | |
| AOC3 | Multiplier factor to set the SCP based on OCP level setting at the ILIM pin | RLDRV = 10 kΩ | 2.75 | 3.2 | 3.6 | V/V |
| AOC7 | RLDRV = open | 6.4 | 7.25 | 7.91 | V/V | |
| AOC15 | RLDRV = 20 kΩ | 13.9 | 16.4 | 18 | V/V | |
| THERMAL SHUTDOWN | ||||||
| TSD,set(1) | Thermal shutdown set threshold | 4.5 V < VVIN < 60 V | 155 | 165 | 175 | °C |
| TSD,reset(1) | Thermal shutdown reset threshold | 125 | 135 | 145 | °C | |
| Thyst(1) | Thermal shutdown hysteresis | 30 | °C | |||
| POWER GOOD | ||||||
| VOV | FB pin voltage upper limit for power good | 4.5 V < VVIN < 60 V | 627 | 647 | 670 | mV |
| VUV | FB pin voltage lower limit for power good | 527 | 552 | 570 | ||
| VPG,HYST | Power good hysteresis voltage at FB pin | 8.5 | 20 | 32 | ||
| VPG(out) | PGOOD pin voltage when FB pin voltage > VOV or < VUV, IPGD = 2 mA | 100 | mV | |||
| VPG(np) | PGOOD pin voltage when device power is removed | VVIN is open, 10-kΩ to VEXT = 5 V | 1 | 1.5 | V | |
| BOOT DIODE | ||||||
| VDFWD | Bootstrap diode forward voltage | I = 20 mA | 0.5 | 0.7 | 0.9 | V |
| RBOOT-SW | Discharge resistor from BOOT to SW | 1 | MΩ | |||