10.1 Layout Guidelines

• Keep the AC current loops as short as possible. For the maximum effectiveness from C3, place it near the VDD pin of the controller and design the input AC loop consisting of C1-R_SENSE-Q1-D1 to be as short as possible. Excessive high frequency noise on VDD during switching degrades overall regulation as the load increases.
• Keep the output loop A (D1-L1-C2) as small as possible. A larger loop can degrade the application output noise performance.
• Traces carrying large AC currents should NOT be connected through a ground plane. Instead, use PCB traces on the top layer to conduct the AC current and use the ground plane as a noise shield. Split the ground plane as necessary to keep noise away from the TPS40200 and noise sensitive areas such as feedback resistors R6, and R10.
• Keep the SW node as physically small as possible to minimize parasitic capacitance and to minimize radiated emissions.
• For good output voltage regulation, Kelvin connections should be brought from the load to R6 and R10.
• The trace from the R6-R10 junction to the TPS40200 should be short and kept away from any noise source (such as the SW node).
• The gate drive trace should be as close as possible to the power FET gate.

10.2 Layout Example

Figure 49. PC Board Layout Recommendations