The soft-start feature of the TPS40210 and TPS40211 is a closed-loop soft start, meaning that the output voltage follows a linear ramp that is proportional to the ramp generated at the SS pin. This ramp is generated by an internal resistor connected from the BP pin to the SS pin and an external capacitor connected from the SS pin to GND. The SS pin voltage (V_SS) is level shifted down by approximately V_SS(ofst) (approximately 700 mV) and sent to one of the “+” (the “+” input with the lowest voltage dominates) inputs of the error amplifier. When this level shifted voltage (V_SSE) starts to rise at time t₁ (see Figure 7-1), the output voltage the controller expects, rises as well. Since V_SSE starts at near 0 V, the controller attempts to regulate the output voltage from a starting point of zero volts. It cannot do this due to the converter architecture. The output voltage starts from the input voltage less the drop across the diode (V_IN - V_D) and rises from there. The point at which the output voltage starts to rise (t₂) is the point where the V_SSE ramp passes the point where it is commanding more output voltage than (V_IN - V_D). This voltage level is labeled V_SSE(1). The time required for the output voltage to ramp from a theoretical zero to the final regulated value (from t₁ to t₃) is determined by the time it takes for the capacitor connected to the SS pin (C_SS) to rise through a 700-mV range, beginning at V_SS(ofst) above GND.

Figure 7-1 SS Pin Voltage and Output Voltage

Figure 7-2 SS Pin Functional Circuit

The required capacitance for a given soft-start time t₃ – t₁ in Figure 7-1 is calculated in Equation 1.

Equation 1.

where

• t_SS is the soft-start time, in seconds
• R_SS(chg) is the SS charging resistance in Ω, typically 500 kΩ
• C_SS is the value of the capacitor on the SS pin, in F
• V_BP is the value of the voltage on the BP pin, in V
• V_SS(ofst) is the approximate level shift from the SS pin to the error amplifier (~700 mV)
• V_FB is the error amplifier reference voltage, 700 mV typical

Note that t_SS is the time it takes for the output voltage to rise from 0 V to the final output voltage. Also note the tolerance on R_SS(chg) given in the Section 6.5. This contributes to some variability in the output voltage rise time and margin must be applied to account for it in design.

Also take note of V_BP. Its value varies depending on input conditions. For example, a converter operating from a slowly rising input initializes V_BP at a fairly low value and increases during the entire startup sequence. If the controller has a voltage above 8 V at the input and the DIS pin is used to stop and then restart the converter, V_BP is approximately 8 V for the entire start-up sequence. The higher the voltage on BP, the shorter the start-up time is and conversely, the lower the voltage on BP, the longer the start-up time is.

The soft-start time (t_SS) must be chosen long enough so that the converter can start up without going into an overcurrent state. Since the over current state is triggered by sensing the peak voltage on the ISNS pin, that voltage must be kept below the overcurrent threshold voltage V_ISNS(oc). The voltage on the ISNS pin is a function of the load current of the converter, the rate of rise of the output voltage and the output capacitance, and the current sensing resistor. The total output current that must be supported by the converter is the sum of the charging current required by the output capacitor and any external load that must be supplied during start-up. This current must be less than the I_OUT(oc) value used in Equation 15 or Equation 16 (depending on the operating mode of the converter) to determine the current sense resistor value. In these equations, the actual input voltage at the time that the controller reaches the final output voltage is the important input voltage to use in the calculations. If the input voltage is slowly rising and is at less than the nominal input voltage when the start-up time ends, the output current limit is less than I_OUT(oc) at the nominal input voltage. The output capacitor charging current must be reduced (decrease C_OUT or increase the t_SS) or I_OUT(oc) must be increased and a new value for R_ISNS calculated.

Equation 2.

Equation 3.

where

• I_C(chg) is the output capacitor charging current in A
• C_OUT is the total output capacitance in F
• V_OUT is the output voltage in V
• t_SS is the soft-start time from Equation 1
• I_OUT(oc) is the desired over current trip point in A
• I_EXT is any external load current in A

The capacitor on the SS pin (C_SS) also plays a role in overcurrent functionality. It is used as the timer between restart attempts. The SS pin is connected to GND through a resistor, R_SS(dchg), whenever the controller senses an overcurrent condition. Switching stops and nothing else happens until the SS pin discharges to the soft-start reset threshold, V_SS(rst). At this point, the SS pin capacitor is allowed to charge again through the charging resistor R_SS(chg), and the controller restarts from that point. The shortest time between restart attempts occurs when the SS pin discharges from V_SS(ofst) (approximately 700 mV) to V_SS(rst) (150 mV) and then back to V_SS(ofst) and switching resumes. In actuality, this is a conservative estimate since switching does not resume until the V_SSE ramp rises to a point where it is commanding more output voltage than exists at the output of the controller. This occurs at some SS pin voltage greater than V_SS(ofst) and depends on the voltage that remains on the output overvoltage the converter while switching has been halted. The fastest restart time can be calculated by using Equation 4, Equation 5, and Equation 6.

Equation 4.

Equation 5.

Equation 6.

Figure 7-3 Soft Start during Overcurrent