The TPS40210-Q1 and TPS40211-Q1 devices have an on-board linear regulator that supplies power for the internal circuitry of the controller, including the gate driver. This regulator has a nominal output voltage of 8 V and must be bypassed with a 1-μF capacitor. If the voltage at the V_DD pin is less than 8 V, the voltage on the BP pin is also less, and the gate drive voltage to the external FET is reduced from the nominal 8 V. This should be considered when choosing a FET for the converter.

Connecting external loads to this regulator can be done, but care must be taken to ensure that the thermal rating of the device is observed, because there is no thermal shutdown feature in this controller. Exceeding the thermal ratings causes out-of-specification behavior and can lead to reduced reliability. The controller dissipates more power when there is an external load on the BP pin and is tested for dropout voltage for up to 5-mA load. When the controller is in the disabled state, the BP pin regulator also shuts off so loads connected there power down as well. When the controller is disabled with the DIS/ EN pin, this regulator is turned off.

The total power dissipation in the controller can be calculated as follows. The total power is the sum of P_Q, P_G, and P_E.

Equation 18.

Equation 19.

Equation 20.

where

• P_Q is the quiescent power of the device in W
• V_DD is the V_DD pin voltage in V
• I_DD(en) is the quiescent current of the controller when enabled but not switching in A
• P_G is the power dissipated by driving the gate of the FET in W
• Q_g is the total gate charge of the FET at the voltage on the BP pin in C
• f_SW is the switching frequency in Hz
• P_E is the dissipation caused be external loading of the BP pin in W
• I_EXT is the external load current in A