A circuit in the TPS4022 device prevents current from being pulled from the output during the start-up sequence in a pre-biased output condition. There are no PWM pulses until the internal soft-start voltage rises above the error amplifier input (FBx pin), if the output is pre-biased. As soon as the soft-start voltage exceeds the error amplifier input, the device slowly initiates synchronous rectification by starting the synchronous rectifier with a narrow on-time. It then increments that on-time on a cycle-by-cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This approach prevents the sinking of current from a pre-biased output, and ensures the output voltage start-up and ramp-to-regulation sequences are smooth and controlled.