TPS4306x 低静态电流同步升压 DC-DC 控制器，支持宽 VIN 范围

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1 特性

58V 最大输出电压
V_IN 范围：4.5V 至 38V（绝对最大值为 40V）
TPS43060：针对标准阈值 MOSFET 优化的 7.5V 栅极驱动器
TPS43061：针对低 Q_g 优化的 5.5V 栅极驱动器 NexFET™功率 MOSFET
支持内部斜率补偿的电流模式控制
可调频率范围：50kHz 至 1MHz
同步外部时钟功能
可调软启动时间
电感器直流电阻 (DCR) 或电阻器电流感测
输出电压电源正常指示器
±0.8% 反馈基准电压
5µA 关断电源电流
600µA 静态工作电流
集成引导加载二极管 (TPS43061)
逐周期电流限制和热关断
可调节的欠压闭锁 (UVLO) 和输出过压保护
小型 16 引脚 WQFN (3mm × 3mm) 封装，带有 PowerPAD™
运行 T_J范围：–40°C 至 150°C

2 应用

用于 PC 的 Thunderbolt 端口
汽车电源系统
同步回扫
氮化镓 (GaN) 射频 (RF) 功率放大器
平板笔记本附件
电池供电系统
5V、12V 和 24V 直流总线电源系统

3 说明

TPS43060 和 TPS43061 是低 I_Q 电流模式同步升压控制器，支持 4.5V 至 38V（绝对最大值为 40V）的宽输入电压范围和高达 58V 的升压输出范围。同步整流功能可为高电流应用实现高效率，无损电感直流电阻 (DCR) 感测功能可进一步提升效率。该器件产生的功率损耗较低，并且采用带 PowerPAD™的 3mm × 3mm WQFN-16 封装，可以在扩展级温度范围（-40°C 至 150°C）内支持高功率密度且高可靠性的升压转换器解决方案。

TPS43060 含有一个 7.5V 栅极驱动电源，适合驱动各种 MOSFET。TPS43061 具有一个 5.5V 栅极驱动电源，驱动强度针对低 Q_g NexFET 功率 MOSFET 进行了优化。另外，TPS43061 为高侧栅极驱动器提供了一个集成型自举二极管，从而减少了外部部件数量。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
TPS43060	RTE (16)	3.00mm × 3.00mm
TPS43061	RTE (16)	3.00mm × 3.00mm

要了解所有可用封装，请见数据表末尾的可订购米6体育平台手机版_好二三四附录。

4 简化电路原理图

TPS43060 TPS43061 Pg1_TPS4060_and_optional_TPS43061_Block_Diagram_SLVSBP4.gif

5 修订历史记录

Changes from C Revision (September 2013) to D Revision

已添加处理额定值表，特性描述部分，器件功能模式，应用和实施部分，电源相关建议部分，布局部分，器件和文档支持部分以及机械、封装和可订购信息部分Go

Changes from B Revision (August 2013) to C Revision

Changed Equation 3Go
Deleted sections Layout Considerations and Thermal ConsiderationsGo
Changed Equation 13 from Dmin to (1-Dmax), 60% to (1-60%) and 2.4 MHz to 1.6 MHzGo
Changed 2 MHz to 1.6 MHz in para below Equation 13Go
Changed in Equation 28 – DS(on)LS to DS(on)HSGo
Changed in Equation 29 – from (60 ns + 65 ns) to (65 ns _65 ns)Go
Changed in paragraph above Equation 37 - 1.93 kHz to 0.97 kHzGo
Changed in Equation 38 – from 1.93 kHz to 0.97 kHzGo
Changed in paragraph above Equation 43 – 7.44 kΩ to 7.45 kΩGo
Changed in Equation 43 – 21 µF to 22 µF, 20 mΩ to 10 mΩ, 19.3 kHz to 14.5 kHz, = 7.44 to = 7.45, and deleted 3/40 factor from denominatorGo

Changes from A Revision (December 2012) to B Revision

已统一整篇数据表的封装说明。Go
Removed ordering information table.Go

Changes from * Revision (December 2012) to A Revision

已将器件从“预览”更改为“量产”Go

6 Pin Configuration and Functions

WQFN-16 PACKAGE

(TOP VIEW)

TPS43060 TPS43061 Pin_Assignments_SLVSBP4.gif

Pin Functions

PIN		DESCRIPTION
NAME	NO.	DESCRIPTION
RT/CLK	1	Resistor timing and external clock. An external resistor from this pin to the AGND pin programs the switching frequency between 50 kHz and 1 MHz. Driving the pin with an external clock between 300 kHz to 1 MHz synchronizes the switching frequency to the external clock.
SS	2	Soft-start programming pin. A capacitor between the SS pin and AGND pin sets soft-start time.
COMP	3	Output of the internal transconductance error amplifier. The feedback loop compensation network is connected from this pin to AGND.
FB	4	Error amplifier input and feedback pin for voltage regulation. Connect this pin to the center tap of a resistor divider to set the output voltage.
ISNS–	5	Inductor current sense comparator inverting input pin. This pin is normally connected to the inductor side of the current sense resistor.
ISNS+	6	Inductor current sense comparator non-inverting input pin. This pin is normally connected to the VIN side of the current sense resistor.
VIN	7	The input supply pin to the IC. Connect VIN to a supply voltage between 4.5 and 38 V. It is acceptable for the voltage on the VIN pin to be different from the boost power stage input, ISNS+, and ISNS– pins.
LDRV	8	Low-side gate driver output. Connect this pin to the gate of the low-side N-channel MOSFET. When VIN bias is removed, an internal 200-kΩ resistor pulls LDRV to PGND.
PGND	9	Power ground of the IC. Connect this pin to the source of the low-side MOSFET. PGND should be connected to AGND via a single point on the PCB.
VCC	10	Output of an internal LDO and power supply for internal control circuits and gate drivers. VCC is typically 7.5 V for the TPS43060 and 5.5 V for the TPS43061. Connect a low-ESR ceramic capacitor from this pin to PGND. TI recommends a capacitance range from 0.47 to 10 µF.
BOOT	11	Bootstrap capacitor node for high-side MOSFET gate driver. Connect the bootstrap capacitor from this pin to the SW pin. For the TPS43060, also connect a bootstrap diode from VCC to BOOT.
SW	12	Switching node of the boost converter. Connect this pin to the junction of the drain of the low-side MOSFET, the source of high-side synchronous MOSFET, and the inductor.
HDRV	13	High-side gate driver output. Connect this pin to the gate of the high-side synchronous rectifier MOSFET. When VIN bias is removed, this pin is connected to SW through an internal 200-kΩ resistor.
PGOOD	14	Power good indicator. This pin is an open-drain output. TI recommends a 10-kΩ pullup resistor between PGOOD and VCC or an external logic supply pin.
EN	15	Enable pin with internal pullup current source. Floating this pin will enable the IC. Pull below 1.2 V to enter low current standby mode. Pull below 0.4 V to enter shutdown mode. The EN pin can be used to implement adjustable UVLO using two resistors.
AGND	16	Analog signal ground of the IC. AGND should be connected to PGND at a single point on the PCB.
PowerPAD	17	The PowerPAD should be connected to AGND. If possible, use thermal vias to connect to an internal ground plane for improved power dissipation.

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)

		MIN	MAX	UNIT
Voltage	Input: VIN, EN, ISNS+, ISNS–	–0.3	40	V
	DC voltage: SW	–0.6	60	V
	Transient voltage (10 ns max): SW	–2	60	V
	FB, RT/CLK, COMP, SS	–0.3	3.6	V
	BOOT, HDRV voltage with respect to ground		65	V
	BOOT, HDRV voltage with respect to SW pin		8	V
	VCC, PGOOD, LDRV	–0.3	8	V
Operating junction temperature		–40	150	°C

7.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–65	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	–2000	2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	–500	500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Input voltage range	4.5	38	V
V_OUT	Output voltage range	V_IN	58	V
V_EN	EN voltage range	0	38	V
V_CLK	External switching frequency logic input range	0	3.6	V
T_J	Operating junction temperature	–40	150	°C

7.4 Thermal Characteristics

over operating free-air temperature range (unless otherwise noted)

THERMAL METRIC ⁽¹⁾		WQFN (16-PINS)	UNIT
R_θJA	Junction-to-ambient thermal resistance	65.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	42.3
R_θJB	Junction-to-board thermal resistance	18
ψ_JT	Junction-to-top characterization parameter	0.9
ψ_JB	Junction-to-board characterization parameter	17.9
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	22.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

V_IN = 4.5 to 38 V, T_J = –40ºC to 150ºC, unless otherwise noted. Typical values are at T_A = 25ºC

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY AND ENABLE
V_IN	Input voltage range			4.5		38	V
V_UV	Input undervoltage threshold		V_IN falling	3.7	3.9	4	V
V_UV	Input undervoltage threshold		V_IN rising	3.9	4.1	4.3	V
V_hys	Undervoltage lockout hysteresis				200		mV
I_Q	Operating quiescent current into V_IN		Device non-switching, R_T = 115 kΩ, V_FB = 2 V		600	800	µA
I_SD	Shutdown current		V_EN = 0.4 V		1.5	5	µA
V_EN	EN pin voltage threshold to standby		V_EN ramping down	0.4	0.7	0.9	V
	EN pin voltage threshold to enable the device		V_EN ramping up	1.12	1.21	1.29	V
	EN pin voltage threshold to disable the device		V_EN ramping down	1	1.14	1.28	V
I_EN	EN pin pullup current		V_EN = 1 V		1.8		µA
I_EN	EN pin hysteresis current		V_EN= 1.3 V		3.2	4.6	µA
t_EN	EN to start switching time		C_VCC = 0.47 µF		125		µs
V_CC	V_CC voltage	TPS43060	V_IN = 12 to 38 V, I_VCC = 0 µA		7.5		V
		TPS43060	V_IN = 4.5 V, I_VCC = 0 µA		4.5		V
		TPS43061	V_IN = 12 to 38 V, I_VCC = 0 µA		5.5		V
		TPS43061	V_IN = 4.5 V, I_VCC = 0 µA		4.5		V
I_VCC	V_CC pin maximum output current			50			mA
VOLTAGE REFERENCE AND ERROR AMPLIFIER
V_REF	Feedback voltage reference		T_J = 25°C	1.21	1.22	1.23	V
V_REF	Feedback voltage reference		T_J = –40°C to 150°C	1.195	1.22	1.244
I_FB	Error amplifier input bias current				20		nA
I_COMP	COMP pin sink current		V_FB = V_REF + 250 mV, V_COMP = 1.5 V		160		µA
I_COMP	COMP pin source current		V_FB = V_REF – 250 mV, V_COMP = 1.5 V		160		µA
V_CLAMP	COMP pin clamp voltage		High clamp, V_FB = 1 V		2.1		V
	COMP pin clamp voltage		Low clamp, V_FB = 1.5 V		0.7
	COMP pin threshold		Duty cycle = 0%		1		V
G_ea	Error amplifier transconductance				1.1		mS
R_ea	Error amplifier output resistance				10		MΩ
F_ea	Error amplifier crossover frequency				2		MHz
CURRENT SENSE
V_CSmax	Maximum current sense threshold		At 0% duty cycle	64	73	82	mV
V_CSmax	Maximum current sense threshold		At max duty cycle	50	61	72	mV
V_RCsns	Reverse current sense threshold				3.8		mV
I_SNS+	Sense+ pin current				70		µA
I_SNS–	Sense– pin current				70		µA
RT/CLK
ƒ_SW	Switching frequency		Operating frequency range using resistor timing mode	50		1000	kHz
			R_T = 115 kΩ	450	500	550	kHz
			R_T = 75 kΩ	675	750	825	kHz
V_RT/CLK	RT/CLK pin voltage				0.5		V
t_CLK-min	Minimum input clock pulse duration		P_LL = 500 kHz		14	60	ns
v_CLK-H	RT/CLK high threshold				1.78	2	V
ƒ_CLK	RT/CLK low threshold			0.4	1.35		V
ƒ_CLK	PLL frequency sync range			300		1000	kHz
t_PLLIN	PLL lock in time				100	250	µs
t_PLLEXIT	Last RT/CLK falling edge to return to resistor timing mode if CLK is not present				140	250	µs
POWER SWITCH DRIVERS
R_LDRV	LDRV pullup resistance	TPS43060	V_IN = 12 to 40 V		2		Ω
		TPS43060	V_IN = 4.5 V		3		Ω
		TPS43061	V_IN = 12 to 40 V		2.5		Ω
		TPS43061	V_IN = 4.5 V		3		Ω
	LDRV pulldown resistance	TPS43060	V_IN = 12 to 40 V		1.2		Ω
		TPS43060	V_IN = 4.5 V		2		Ω
		TPS43061	V_IN = 12 to 40 V		1.6		Ω
		TPS43061	V_IN = 4.5 V		2		Ω
R_HDRV	HDRV pullup resistance	TPS43060	V_IN = 12 to 40 V		2		Ω
		TPS43060	V_IN = 4.5 V		2.8		Ω
		TPS43061	V_IN = 12 to 40 V		5		Ω
		TPS43061	V_IN = 4.5 V		5.5		Ω
	HDRV pulldown resistance	TPS43060	V_IN = 12 to 40 V		1.2		Ω
		TPS43060	V_IN = 4.5 V		1.9		Ω
		TPS43061	V_IN = 12 to 40 V		3		Ω
		TPS43061	V_IN = 4.5 V		3.7		Ω
t_HR	High-side gate rise time, 10% to 90%	TPS43060	C_LOAD = 2.2 nF, V_IN = 12 to 40 V		15		ns
t_HR	High-side gate rise time, 10% to 90%	TPS43061	C_LOAD = 2.2 nF, V_IN = 12 to 40 V		20		ns
t_HF	High-side gate fall time, 90% to 10%	TPS43060	C_LOAD = 2.2 nF, V_IN = 12 to 40 V		10		ns
t_HF	High-side gate fall time, 90% to 10%	TPS43061	C_LOAD = 2.2 nF, V_IN = 12 to 40 V		15		ns
t_LR	Low-side gate rise time, 10% to 90%	TPS43060	C_LOAD = 2.2 nF, V_IN = 12 to 40 V		15		ns
t_LR	Low-side gate rise time, 10% to 90%	TPS43061	C_LOAD = 2.2 nF, V_IN = 12 to 40 V		20		ns
t_LF	Low-side gate fall time, 90% to 10%	TPS43060	C_LOAD = 2.2 nF, V_IN = 12 to 40 V		10		ns
t_LF	Low-side gate fall time, 90% to 10%	TPS43061	C_LOAD = 2.2 nF, V_IN = 12 to 40 V		15		ns
V_F	BOOT diode forward voltage drop	TPS43061	I_F = 10 mA, T_A = 25ºC		0.75		V
I_BOOT	BOOT pin leakage current	TPS43061	V_r = 60 V		0.1		µA
t_ON	LDRV minimum on pulse duration		ƒ_SW = 500 kHz		100		ns
t_OFF	LDRV minimum off pulse duration		ƒ_SW = 500 kHz		250		ns
t_delay	Time delay between LDRV fall(50%) to HDRV rise (50%), t_non-overlap1	TPS43060, C_LOAD = open, ƒ_SW = 500 kHz	V_IN = 12 V		65		ns
		TPS43060, C_LOAD = open, ƒ_SW = 500 kHz	V_IN = 4.5 V		75		ns
		TPS43061, C_LOAD = open, ƒ_SW = 500 kHz	V_IN = 12 V		65		ns
		TPS43061, C_LOAD = open, ƒ_SW = 500 kHz	V_IN = 4.5 V		75		ns
	Time delay between HDRV fall (50%) to LDRV rise (50%), t_non-overlap2	TPS43060, C_LOAD = open, ƒ_SW = 500 kHz	V_IN = 12 V		65		ns
		TPS43060, C_LOAD = open, ƒ_SW = 500 kHz	V_IN = 4.5 V		75		ns
		TPS43061, C_LOAD = open, ƒ_SW = 500 kHz	V_IN = 12 V		65		ns
		TPS43061, C_LOAD = open, ƒ_SW = 500 kHz	V_IN = 4.5 V		75		ns
POWER GOOD, SS AND OVP
P_GDL	PGOOD low threshold		V_FB with respect to feedback voltage reference, V_FB falling	86%	90%	93%
P_GDL	PGOOD low hysteresis		V_FB with respect to feedback voltage reference		2%
P_GDH	PGOOD high threshold		V_FB with respect to feedback voltage reference, V_FB rising	107%	110%	114%
P_GDH	PGOOD high hysteresis		V_FB with respect to feedback voltage reference		2%
P_GDSC	PGOOD sink current		V_PGOOD = 0.4 V	1.8	4		mA
P_GDLK	PGOOD pin leakage current		V_PGOOD = 7 V		100		nA
V_{IN_PGD}	Minimum V_IN for valid PGOOD				2.5	4.3	V
I_SS	Soft-start bias current		V_SS = 0 V		5		µA
R_SS	Soft-start discharge resistance				250		Ω
V_OVP	OVP threshold		V_FB with respect to feedback voltage reference, V_FB rising	104%	107%	110%
V_OVP	OVP hysteresis		V_FB with respect to feedback voltage reference		2%
THERMAL SHUTDOWN
T_SD	Thermal shutdown set threshold				165		°C
T_hyst	Thermal shutdown hysteresis				15		°C