11.1 Layout Guidelines

Layout is a critical portion of a good power converter design. Several signal paths that conduct fast changing currents or voltages can interact with stray inductance or parasitic capacitance to generate noise or degrade performance. Guidelines are as follows, and the EVM layouts can be used as a reference.

• The high-speed switching current path includes the high-side FET, low-side FET, and output capacitors. This is a critical loop to minimize in order to reduce noise and achieve best performance.
• Components connected to noise-sensitive circuitry should be located as close to the TPS4306x as possible, and be connected the AGND pin. This includes components connected to FB, COMP, SS, and RT/CLK pins.
• The PowerPAD should be connected to the quiet analog ground for the AGND pin to limit internal noise. For thermal performance, multiple vias directly under the device should be used to connect to any internal ground planes.
• Components in the power conversion path should be connected to the PGND. This includes the bulk input capacitors, output capacitors, low-side FET, and EN UVLO resistors.
• A single connection must connect the quiet AGND to the noisy PGND near the PGND pin.
• The low-ESR ceramic bypass capacitor for the VIN pin should be connected to the quiet AGND as close as possible to the TPS4306x.
• The distance between the inductor, low-side FET, and high-side FET should be minimized to reduce noise. This connection is the high-speed switching voltage node.
• The high-side and low-side FETs should be placed close to the device to limit the trace length required for the HDRV and LDRV gate drive signals.
• The bypass capacitor between the ISNS+ and ISNS– pins should be placed next to the TPS4306x. Minimize the distance between the device and the sense resistors.

11.2 Layout Example

11.3 Thermal Considerations

The TPS4306x junction temperature should not exceed 150°C under normal operating conditions. This restriction limits the power dissipation of the device. Power dissipation of the controller includes gate drive power loss and bias power loss of the internal VCC regulator. The TPS4306x is packaged in a thermally-enhanced WQFN package, which includes a PowerPAD that improves the thermal capabilities. The thermal resistance of the WQFN package depends on the PCB layout and the PowerPAD connection. As mentioned in the layout considerations, the PowerPAD must be soldered to the analog ground on the PCB with thermal vias underneath the PowerPAD to achieve good thermal performance.

For best thermal performance, PCB copper area should be sized to improve thermal capabilities of the components in the power path dissipating the most power. This includes the sense resistors, inductor, low-side FET, and high-side FET. Follow the manufacturer guidelines for the selected external FETs.