SLVSB48C August   2012  – July 2016 TPS43333-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Typical Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Buck Controllers: Normal Mode PWM Operation
        1. 7.3.1.1 Frequency Selection and External Synchronization
        2. 7.3.1.2 Enable Inputs
        3. 7.3.1.3 Feedback Inputs
        4. 7.3.1.4 Soft-Start Inputs
        5. 7.3.1.5 Current-Mode Operation
        6. 7.3.1.6 Current Sensing and Current Limit With Foldback
        7. 7.3.1.7 Slope Compensation
        8. 7.3.1.8 Power-Good Outputs and Filter Delays
        9. 7.3.1.9 Light-Load PFM Mode
      2. 7.3.2 Boost Controller
      3. 7.3.3 SYNC Pin
      4. 7.3.4 Gate-Driver Supply (VREG, EXTSUP)
      5. 7.3.5 External P-Channel Drive (GC2) and Reverse-Battery Protection
      6. 7.3.6 Undervoltage Lockout and Overvoltage Protection
      7. 7.3.7 Thermal Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Example 1
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Boost Component Selection
          2. 8.2.1.2.2  Boost Maximum Input Current IIN_MAX
          3. 8.2.1.2.3  Boost Inductor Selection, L
          4. 8.2.1.2.4  Inductor Ripple Current, IRIPPLE
          5. 8.2.1.2.5  Peak Current in Low-Side FET, IPEAK
          6. 8.2.1.2.6  Right Half-Plane Zero RHP Frequency, fRHP
          7. 8.2.1.2.7  Output Capacitor, CO
          8. 8.2.1.2.8  Bandwidth of Boost Converter, fC
          9. 8.2.1.2.9  Output Ripple Voltage Due to Load Transients, ∆VO
          10. 8.2.1.2.10 Selection of Components for Type II Compensation
          11. 8.2.1.2.11 Input Capacitor, CIN
          12. 8.2.1.2.12 Output Schottky Diode D1 Selection
          13. 8.2.1.2.13 Low-Side MOSFET (BOT_SW3)
          14. 8.2.1.2.14 BuckA Component Selection
            1. 8.2.1.2.14.1 Minimum On-Time, tON min
            2. 8.2.1.2.14.2 Current-Sense Resistor RSENSE
          15. 8.2.1.2.15 Inductor Selection L
          16. 8.2.1.2.16 Inductor Ripple Current IRIPPLE
          17. 8.2.1.2.17 Output Capacitor COUT
          18. 8.2.1.2.18 Bandwidth of Buck Converter fC
          19. 8.2.1.2.19 Selection of Components for Type II Compensation
          20. 8.2.1.2.20 Resistor Divider Selection for Setting VOUTA Voltage
          21. 8.2.1.2.21 BuckB Component Selection
          22. 8.2.1.2.22 Resistor Divider Selection for Setting VO Voltage
          23. 8.2.1.2.23 BuckX High-Side and Low-Side N-Channel MOSFETs
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Application Example 2
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Component Proposals
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Boost Converter
      2. 10.1.2 Buck Converter
      3. 10.1.3 Other Considerations
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD Package
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

1 Features

  • Qualified for Automotive Applications
  • AEC-Q100 Test Guidance With the Following Results:
    • Device Temperature Grade 1: –40°C to 125°C Ambient Operating Temperature
    • Device HBM ESD Classification Level H2
    • Device CDM ESD Classification Level C2
  • Two Synchronous Buck Controllers
  • One Pre-Boost Controller
  • Input Range up to 40 V (Transients up to 60 V), Operation Down to 2 V When Boost is Enabled
  • Low-Power-Mode IQ: 30 µA (One Buck On), 35 µA (Two Bucks On)
  • Low-Shutdown Current Ish < 4 µA
  • Buck Output Range 0.9 V to 11 V
  • Boost Output Selectable: 7 V, 10 V, or 11 V
  • Programmable Frequency and External Synchronization Range: 150 kHz to 600 kHz
  • Separate Enable Inputs (ENA, ENB)
  • Selectable Forced-Continuous Mode or Automatic Low-Power Mode at Light Loads
  • Sense Resistor or Inductor DCR Sensing
  • Out-of-Phase Switching Between Buck Channels
  • Peak Gate-Drive Current: 1.5 A
  • Thermally Enhanced 38-Pin HTSSOP (DAP) PowerPAD™ Package

2 Applications

  • Automotive Start-Stop, Infotainment, Navigation Instrument Cluster Systems
  • Industrial and Automotive Multi-Rail DC Power Distribution Systems and Electronic Control Units

3 Description

The TPS43333-Q1 includes two current-mode synchronous buck controllers and a voltage-mode boost controller. The device is ideal for use as a pre-regulator stage with low Iq requirements and for applications that must survive supply drops due to cranking events. The integrated boost controller allows the device to operate down to 2 V at the input without seeing a drop on the buck-regulator output stages. At light loads, one can enable the buck controllers to operate automatically in low-power mode, consuming just 30 µA of quiescent current.

The buck controllers have independent soft-start capability and power-good indicators. Current foldback in the buck controllers and cycle-by-cycle current limitation in the boost controller provide external MOSFET protection. The switching frequency is programmable over 150 kHz to 600 kHz or can synchronize to an external clock in the same range.

Table 1. Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
TPS43333-Q1 HTSSOP (38) 12.50 mm × 6.20 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

3.1 Typical Application Diagram

TPS43333-Q1 simplified_block_dgm_SLVSB48.gif
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