SLVSB48C August   2012  – July 2016 TPS43333-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Typical Application Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Buck Controllers: Normal Mode PWM Operation
        1. 7.3.1.1 Frequency Selection and External Synchronization
        2. 7.3.1.2 Enable Inputs
        3. 7.3.1.3 Feedback Inputs
        4. 7.3.1.4 Soft-Start Inputs
        5. 7.3.1.5 Current-Mode Operation
        6. 7.3.1.6 Current Sensing and Current Limit With Foldback
        7. 7.3.1.7 Slope Compensation
        8. 7.3.1.8 Power-Good Outputs and Filter Delays
        9. 7.3.1.9 Light-Load PFM Mode
      2. 7.3.2 Boost Controller
      3. 7.3.3 SYNC Pin
      4. 7.3.4 Gate-Driver Supply (VREG, EXTSUP)
      5. 7.3.5 External P-Channel Drive (GC2) and Reverse-Battery Protection
      6. 7.3.6 Undervoltage Lockout and Overvoltage Protection
      7. 7.3.7 Thermal Protection
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Application Example 1
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Boost Component Selection
          2. 8.2.1.2.2  Boost Maximum Input Current IIN_MAX
          3. 8.2.1.2.3  Boost Inductor Selection, L
          4. 8.2.1.2.4  Inductor Ripple Current, IRIPPLE
          5. 8.2.1.2.5  Peak Current in Low-Side FET, IPEAK
          6. 8.2.1.2.6  Right Half-Plane Zero RHP Frequency, fRHP
          7. 8.2.1.2.7  Output Capacitor, CO
          8. 8.2.1.2.8  Bandwidth of Boost Converter, fC
          9. 8.2.1.2.9  Output Ripple Voltage Due to Load Transients, ∆VO
          10. 8.2.1.2.10 Selection of Components for Type II Compensation
          11. 8.2.1.2.11 Input Capacitor, CIN
          12. 8.2.1.2.12 Output Schottky Diode D1 Selection
          13. 8.2.1.2.13 Low-Side MOSFET (BOT_SW3)
          14. 8.2.1.2.14 BuckA Component Selection
            1. 8.2.1.2.14.1 Minimum On-Time, tON min
            2. 8.2.1.2.14.2 Current-Sense Resistor RSENSE
          15. 8.2.1.2.15 Inductor Selection L
          16. 8.2.1.2.16 Inductor Ripple Current IRIPPLE
          17. 8.2.1.2.17 Output Capacitor COUT
          18. 8.2.1.2.18 Bandwidth of Buck Converter fC
          19. 8.2.1.2.19 Selection of Components for Type II Compensation
          20. 8.2.1.2.20 Resistor Divider Selection for Setting VOUTA Voltage
          21. 8.2.1.2.21 BuckB Component Selection
          22. 8.2.1.2.22 Resistor Divider Selection for Setting VO Voltage
          23. 8.2.1.2.23 BuckX High-Side and Low-Side N-Channel MOSFETs
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Application Example 2
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 Component Proposals
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Boost Converter
      2. 10.1.2 Buck Converter
      3. 10.1.3 Other Considerations
    2. 10.2 Layout Example
    3. 10.3 Power Dissipation Derating Profile, 38-Pin HTTSOP PowerPAD Package
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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订购信息

6 Specifications

6.1 Absolute Maximum Ratings

All voltage values are with respect to AGND (unless otherwise noted)(1)
MIN MAX UNIT
Voltage Input voltage: VIN, VBAT –0.3 60 V
Voltage
(buck function:
BuckA and BuckB)		 Ground: PGNDA–AGND, PGNDB–AGND –0.3 0.3 V
Enable inputs: ENA, ENB –0.3 60
Bootstrap inputs: CBA, CBB –0.3 68
Bootstrap inputs: CBA–PHA, CBB–PHB –0.3 8.8
Phase inputs: PHA, PHB –0.7 60
Phase inputs: PHA, PHB (for 150 ns) –1 60
Feedback inputs: FBA, FBB –0.3 13
Error amplifier outputs: COMPA, COMPB –0.3 13
High-side MOSFET driver: GA1–PHA, GB1–PHB –0.3 8.8
Low-side MOSFET drivers: GA2–PGNDA, GB2–PGNDB –0.3 8.8
Current-sense voltage: SA1, SA2, SB1, SB2 –0.3 13
Soft start: SSA, SSB –0.3 13
Power-good output: PGA, PGB –0.3 13
Power-good delay: DLYAB –0.3 13
Switching-frequency timing resistor: RT –0.3 13
SYNC, EXTSUP –0.3 13
Voltage
(boost function)		 Low-side MOSFET driver: GC1–PGNDA –0.3 8.8 V
Error-amplifier output: COMPC –0.3 13
Enable input: ENC –0.3 13
Current-limit sense: DS –0.3 60
Output-voltage select: DIV –0.3 8.8
Voltage
(PMOS driver)		 P-channel MOSFET driver: GC2 –0.3 60 V
P-channel MOSFET driver: VIN-GC2 –0.3 8.8
Voltage
(gate-driver supply)		 Gate-driver supply: VREG –0.3 8.8 V
Temperature Junction temperature: TJ –40 150 °C
Operating temperature: TA –40 125
Storage temperature: Tstg –55 165
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 All other pins ±500
Pins FBA, FBB, RT, and DLYAB ±400
Corner pins (VBAT, ENC, SYNC, and VIN) ±750
Machine model (MM) PGA, PGB ±150
All other pins ±200
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Buck function:
BuckA and BuckB voltage		 Input voltage: VIN, VBAT 4 40 V
Enable inputs: ENA, ENB 0 40
Boot inputs: CBA, CBB 4 48
Phase inputs: PHA, PHB –0.6 40
Current-sense voltage: SA1, SA2, SB1, SB2 0 11
Power-good output: PGA, PGB 0 11
SYNC, EXTSUP 0 9
Boost function Enable input: ENC 0 9 V
Voltage sense: DS 40
DIV 0 VREG
Temperature Operating temperature: TA –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TPS43333-Q1 UNIT
DAP (HTSSOP)
38 PINS
RθJA Junction-to-ambient thermal resistance 27.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 19.6 °C/W
RθJB Junction-to-board thermal resistance 15.9 °C/W
ψJT Junction-to-top characterization parameter 0.24 °C/W
ψJB Junction-to-board characterization parameter 6.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

VIN = 8 V to 18 V, TJ = –40°C to 150°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
VBat Supply voltage Boost controller enabled, after satisfying initial start-up condition 2 40 V
VIN Input voltage required for device on initial start-up 6.5 40 V
Buck regulator operating range after initial start-up 4 40
VIN UV Buck undervoltage lockout VIN falling. After a reset, initial start-up conditions may apply.(1) 3.5 3.6 3.8 V
VIN rising. After a reset, initial start-up conditions may apply.(1) 3.8 4
Iq_LPM_ LPM quiescent current(2) VIN = 13 V, BuckA: LPM, BuckB: off, TA = 25°C 30 40 µA
VIN = 13 V, BuckB: LPM, BuckA: off, TA = 25°C 30 40
VIN = 13 V, BuckA, B: LPM, TA = 25°C 35 45 µA
Iq_LPM LPM quiescent current(2) VIN = 13 V, BuckA: LPM, BuckB: off, TA = 125°C 40 50 µA
VIN = 13 V, BuckB: LPM, BuckA: off, TA = 125°C 40 50
VIN = 13 V, BuckA, B: LPM, TA = 125°C 45 55 µA
Iq_NRM Quiescent current:
normal (PWM) mode(2)		 SYNC = 5 V, TA = 25°C 4.85 5.3 mA
VIN = 13 V, BuckA: CCM, BuckB: off, TA = 25°C 4.85 5.3
VIN = 13 V, BuckB: CCM, BuckA: off, TA = 25°C 4.85 5.3
VIN = 13 V, BuckA, B: CCM, TA = 25°C 7 7.6
Iq_NRM Quiescent current:
normal (PWM) mode(2)		 SYNC = 5 V, TA = 125°C 5 5.5 mA
VIN = 13 V, BuckA: CCM, BuckB: off, TA = 125°C 5 5.5
VIN = 13 V, BuckB: CCM, BuckA: off, TA = 125°C 5 5.5
VIN = 13 V, BuckA, B: CCM, TA = 125°C 7.5 8
Ibat_sh Shutdown current BuckA, B: off, VBAT = 13 V , TA = 25°C 2.5 4 µA
Ibat_sh Shutdown current BuckA, B: off, VBAT = 13 V, TA = 125°C 3 5 µA
INPUT VOLTAGE VBAT - UNDERVOLTAGE LOCKOUT
VBATUV Boost-input undervoltage VBAT falling. After a reset, initial start-up conditions may apply.(1) 1.8 1.9 2 V
VBAT rising. After a reset, initial start-up conditions may apply.(1) 2.4 2.5 2.6
UVLOHys Hysteresis 500 600 700 mV
UVLOfilter Filter time 5 µs
INPUT VOLTAGE VIN - OVERVOLTAGE LOCKOUT
VOVLO Overvoltage shutdown VIN rising 45 46 47 V
VIN falling 43 44 45
OVLOHys Hysteresis 1 2 3 V
OVLOfilter Filter time 5 µs
BOOST CONTROLLER
Vboost7-VIN Boost VOUT = 7 V DIV = low, VBAT = 2 V to 7 V 6.8 7 7.3 V
Vboost7-th Boost-enable threshold Boost VOUT = 7 V, VBAT falling 7.5 8 8.5 V
Boost-disable threshold Boost VOUT = 7 V, VBAT rising 8 8.5 9
Boost hysteresis Boost VOUT = 7 V, VBAT rising or falling 0.4 0.5 0.6
Vboost10-VIN Boost VOUT = 10 V DIV = open, VBAT = 2 V to 10 V 9.7 10 10.4 V
Vboost10-th Boost-enable threshold Boost VOUT = 10 V, VBAT falling 10.5 11 11.5 V
Boost-disable threshold Boost VOUT = 10 V, VBAT rising 11 11.5 12
Boost hysteresis Boost VOUT = 10 V, VBAT rising or falling 0.4 0.5 0.6
Vboost11-VIN Boost VOUT = 11 V DIV = VREG, VBAT = 2 V to 11 V 10.7 11 11.4 V
Vboost11-th Boost-enable threshold Boost VOUT = 11 V, VBAT falling 11.5 12 12.5 V
Boost-disable threshold Boost VOUT = 11 V, VBAT rising 12 12.5 13
Boost hysteresis Boost VOUT = 11 V, VBAT rising or falling 0.4 0.5 0.6
BOOST-SWITCH CURRENT LIMIT
VDS Current-limit sensing DS input with respect to PGNDA 0.175 0.2 0.225 V
tDS Leading-edge blanking 200 ns
GATE DRIVER FOR BOOST CONTROLLER
IGC1 Peak Gate-driver peak current 1.5 A
rDS(on) Source and sink driver VREG = 5.8 V, IGC1 current = 200 mA 2 Ω
GATE DRIVER FOR PMOS
rDS(on) PMOS OFF 10 20 Ω
IPMOS_ON Gate current VIN = 13.5 V, VGS = –5 V 10 mA
tdelay_ON Turnon delay C = 10 nF 5 10 µs
BOOST-CONTROLLER SWITCHING FREQUENCY
fsw-Boost Boost switching frequency fSW_Buck / 2 kHz
DBoost Boost duty cycle 90%
ERROR AMPLIFIER (OTA) FOR BOOST CONVERTERS
GmBOOST Forward transconductance VBAT = 12 V 0.8 1.35 mS
VBAT = 5 V 0.35 0.65
BUCK CONTROLLERS
VBuckA/B Adjustable output-voltage range 0.9 11 V
Vref, NRM Internal reference voltage and tolerance in normal mode Measure FBX pin 0.792 0.800 0.808 V
–1% 1%
Vref, LPM Internal reference voltage and tolerance in low-power mode Measure FBX pin 0.784 0.800 0.816 V
–2% 2%
Vsense V sense for forward-current limit in CCM FBx = 0.75 V (low duty cycle) 60 75 90 mV
V sense for reverse-current limit in CCM FBx = 1 V –65 –37.5 –23 mV
VI-Foldback V sense for output short FBx = 0 V 17 32.5 48 mV
tdead Shoot-through delay, blanking time 20 ns
DCNRM High-side minimum on-time 100 ns
Maximum duty cycle (digitally controlled) 98.75%
DCLPM Duty cycle, LPM 80%
ILPM_Entry LPM entry-threshold load current as fraction of maximum set load current 1% See(3)
ILPM_Exit LPM exit-threshold load current as fraction of maximum set load current See(3) 10%
HIGH-SIDE EXTERNAL NMOS GATE DRIVERS FOR BUCK CONTROLLER
IGX1_peak Gate-driver peak current 1.5 A
rDS(on) Source and sink driver VREG = 5.8 V, IGX1 current = 200 mA 2 Ω
LOW-SIDE NMOS GATE DRIVERS FOR BUCK CONTROLLER
IGX2_peak Gate driver peak current 1.5 A
RDS ON Source and sink driver VREG = 5.8 V, IGX2 current = 200 mA 2 Ω
ERROR AMPLIFIER (OTA) FOR BUCK CONVERTERS
GmBUCK Transconductance COMPA, COMPB = 0.8 V,
source/sink = 5 µA, test in feedback loop		 0.72 1 1.35 mS
IPULLUP_FBx Pullup current at FBx pins FBx = 0 V 50 100 200 nA
DIGITAL INPUTS: ENA, ENB, ENC, SYNC
VIH Higher threshold VIN = 13 V 1.7 V
VIL Lower threshold VIN = 13 V 0.7 V
RIH_SYNC Pulldown resistance on SYNC VSYNC = 5 V 500 kΩ
RIL_ENC Pulldown resistance on ENC VENC = 5 V 500 kΩ
IIL_ENx Pullup current source on ENA, ENB VENx = 0 V, 0.5 2 µA
BOOST OUTPUT VOLTAGE: DIV
VIH_DIV Higher threshold VREG = 5.8 V VREG – 0.2 V
VIL_DIV Lower threshold 0.2 V
Voz_DIV Voltage on DIV if unconnected Voltage on DIV if unconnected VREG / 2 V
SWITCHING PARAMETER – BUCK DC-DC CONTROLLERS
fSW_Buck Buck switching frequency RT pin: GND 360 400 440 kHz
fSW_Buck Buck switching frequency RT pin: 60-kΩ external resistor 360 400 440 kHz
fSW_adj Buck adjustable range with external resistor RT pin: external resistor 150 600 kHz
fSYNC Buck synchronization range External clock input 150 600 kHz
INTERNAL GATE-DRIVER SUPPLY
VREG Internal regulated supply VIN = 8 V to 18 V, EXTSUP = 0 V, SYNC = high 5.5 5.8 6.1 V
Load regulation IVREG = 0 mA to 100 mA, EXTSUP = 0 V,
SYNC = high		 0.2% 1%
VREG(EXTSUP) Internal regulated supply EXTSUP = 8.5 V 7.2 7.5 7.8 V
Load regulation IEXTSUP = 0 mA to 125 mA, SYNC = High
EXTSUP = 8.5 V to 13 V		 0.2% 1%
VEXTSUP-th EXTSUP switch-over voltage threshold IVREG = 0 mA to 100 mA,
EXTSUP ramping positive		 4.4 4.6 4.8 V
VEXTSUP-Hys EXTSUP switch-over hysteresis 150 250 mV
IREG-Limit Current limit on VREG EXTSUP = 0 V, normal mode as well as LPM 100 400 mA
IREG_EXTSUP-Limit Current limit on VREG when using EXTSUP IVREG = 0 mA to 100 mA,
EXTSUP = 8.5 V, SYNC = High		 125 400 mA
SOFT START
ISSx Soft-start source current SSA and SSB = 0 V 0.75 1 1.25 µA
OSCILLATOR (RT)
VRT Oscillator reference voltage 1.2 V
POWER GOOD / DELAY
PGpullup Pullup for A and B to Sx2 50 kΩ
PGth1 Power-good threshold FBx falling –5% –7% –9%
PGhys Hysteresis 2%
PGdrop Voltage drop IPGA = 5 mA 450 mV
IPGA = 1 mA 100 mV
PGleak Power-good leakage VSx2 = VPGx = 13 V 1 µA
tdeglitch Power-good deglitch time 2 16 µs
tdelay Reset delay External capacitor = 1 nF
VBUCKX < PGth1		 1 ms
tdelay_fix Fixed reset delay No external capacitor, pin open 20 50 µs
IOH Activate current source (current to charge external capacitor) 30 40 50 µA
IIL Activate current sink (current to discharge external capacitor) 30 40 50 µA
OVERTEMPERATURE PROTECTION
Tshutdown Junction-temperature shutdown threshold 150 165 °C
Thys Junction-temperature hysteresis 15 °C
(1) If VBAT and VREG remain adequate, the buck can continue to operate if VIN is > 3.8 V.
(2) Quiescent current specification is non-switching current consumption without including the current in the external-feedback resistor divider.
(3) The exit threshold specification is to be always higher than the entry threshold.

6.6 Typical Characteristics

TPS43333-Q1 g_efficiency_across_output_currents_buck_lvsa82.gif
VIN = 12 V VOUT = 5 V fSW = 400 kHz
L = 4.7 µH RSENSE = 10 mΩ
Figure 1. Efficiency Across Output Currents (Bucks)
TPS43333-Q1 g_buck_load_step_forced_cont_lvsa82.gif
VIN = 12 V VOUT = 5 V fSW = 400 kHz
L = 4.7 µH RSENSE = 10 mΩ
Figure 3. Buck Load Step: Forced Continuous Mode,
0 to 4 A At 2.5 A/µs
TPS43333-Q1 g_buck_load_step_low_power_entry_lvsa82.gif
VIN = 12 V VOUT = 5 V fSW = 400 kHz
L = 4.7 µH RSENSE = 10 mΩ
Figure 5. Buck Load Step: Low-Power-Mode Entry,
4 A to 90 mA at 2.5 A/µs
TPS43333-Q1 g_efficiency_across_output_currents_boost_slvsb48.gif
VIN = 10 V fSW = 200 kHz
L = 1 µH RSENSE = 7.5 mΩ
Figure 7. Efficiency Across Temperature
TPS43333-Q1 g_cranking_pulse_boost_response_12v_3v_slvsb48.gif
VIN = 10 V BuckA 5 V
at 1.5 A 		BuckB = 3.3 V
at 3.5 A
fSW = 200 kHz L = µH,
RSENSE = 7.5 mΩ 		CIN = 440 µF,
COUT = 660 µF
Figure 9. Cranking-Pulse Boost Response (12 V to 3 V
in 1 ms at Buck Outputs 7.5 W and 11.5 W)
TPS43333-Q1 g_inductor_currents_boost_slvsb48.gif
VBAT = 5 V,
VIN = 10 V 		fSW = 200 kHz L = 1 µH
RSENSE = 7.5 mΩ CIN = 440 µF COUT = 660 µF
Figure 11. Inductor Currents (Boost)
TPS43333-Q1 g_current_limit_vs_compx_voltage_buck_lvsa82.gif Figure 13. BUCKx Peak Current Limit vs COMPx
TPS43333-Q1 g_foldback_current_limit_buck_lvsa82.gif Figure 15. Foldback Current Limit (Buck)
TPS43333-Q1 g_current_limit_duty_cycle_buck_lvsa82.gif Figure 17. Peak Current Sense Voltage vs Duty Cycle
TPS43333-Q1 g_inductor_current_buck_lvsa82.gif
VIN = 12 V VOUT = 5 V fSW = 400 kHz
L = 4.7 µH RSENSE = 10 mΩ
Figure 2. Inductor Currents (Buck)
TPS43333-Q1 BUCK_LOAD_STEP_FORCED_SLVSC16_inverted.gif
Figure 4. Soft-Start Outputs (Buck)
TPS43333-Q1 g_buck_load_step_low_power_exit_lvsa82.gif
VIN = 12 V VOUT = 5 V fSW = 400 kHz
L = 4.7 µH RSENSE = 10 mΩ
Figure 6. Buck Load Step: Low-Power-Mode Exit,
90 mA to 4 A at 2.5 A/µs
TPS43333-Q1 C001_SLVSC16_inverted1_slvsb48.gif
VBAT = 5 V,
VIN = 10 V 		fSW = 200 kHz L = 680 nH
RSENSE = 10 mΩ CIN = 440 µF COUT = 660 µF
Figure 8. Load Step Response (Boost)
(0 A to 5 A at 10 A/µs)
TPS43333-Q1 g_cranking_pulse_boost_response_12v_4v_slvsb48.gif
VIN = 10 V BuckA = 5 V
at 1.5 A 		BuckB = 3.3 V
at 3.5 A
fSW = 200 kHz L = 1 µH,
RSENSE = 7.5 mΩ 		CIN = 440 µF,
COUT = 660 µF
Figure 10. Cranking-Pulse Boost Response (12 V to 4 V
in 1 ms at Boost Direct Output 25 W)
TPS43333-Q1 g_no_load_iq_over_temp_misc_lvsa82.gif
Figure 12. No-Load Quiescent Current Across Temperature
TPS43333-Q1 g_current_sense_pins_input_current_buck_lvsa82.gif Figure 14. Current-Sense Pins Input Current (Buck)
TPS43333-Q1 g_regulated_fbx_voltage_temp_buck_lvsa82.gif Figure 16. Regulated FBx Voltage vs Temperature
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