For limiting inrush current during turn-ON of the external FET (Q1) with capacitive loads, use R₁, R₂, C₁ as shown in Figure 7-4. The R₁ and C₁ components slow down the voltage ramp rate at the gate of Q1 FET. The FET source follows the gate voltage resulting in a controlled voltage ramp across the output capacitors.

Figure 7-4 Inrush Current Limiting Using G1 Gate Drive

Use the Equation 2 to calculate the inrush current during turn-ON of the FET.

Where,

C_LOAD is the load capacitance.

VBATT is the input voltage and T_charge is the charge time.

V_(BST-SRC) is the charge pump voltage (11V),

Use a damping resistor R₂ (approximately 10Ω) in series with C₁. Equation 3 can be used to compute required C₁ value for a target inrush current. A 100kΩ resistor for R₁ can be a good starting point for calculations.

Connecting G1PD pin of TPS48100-Q1 directly to the gate of the Q1 FET ensures fast turn-OFF without any impact of R₁ and C₁ components.

C₁ results in an additional loading on C_BST to charge during turn-ON. Use below equation to calculate the required C_BST value:

Where,

Q_g(total) is the total gate charge of the FET,

ΔV_BST (1V typical) is the ripple voltage across BST to SRC pins.