ZHCSQE1 January 2024 TPS4810-Q1
ADVANCE INFORMATION
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Parameter Measurement Information
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, G2, BST, SRC)
- 7.3.2 Capacitive Load Driving Using FET Gate (G1PU, G1PD) Slew Rate Control
- 7.3.3 Short-Circuit Protection
- 7.3.4 Undervoltage Protection (UVLO)
- 7.3.5 Reverse Polarity Protection
- 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
- 7.3.7 TPS48100-Q1 as a Simple Gate Driver
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
7.3.4 Undervoltage Protection (UVLO)
TPS48100-Q1 has an accurate undervoltage protection (< ±2%) using EN/UVLO pin providing robust protection. Connect a resistor ladder as shown in Figure 7-10 for undervoltage protection threshold programming.
Figure 7-10 Programming Undervoltage Protection