ZHCSQE1 January 2024 TPS4810-Q1
ADVANCE INFORMATION
- 1
- 1 特性
- 2 应用
- 3 说明
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Parameter Measurement Information
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, G2, BST, SRC)
- 7.3.2 Capacitive Load Driving Using FET Gate (G1PU, G1PD) Slew Rate Control
- 7.3.3 Short-Circuit Protection
- 7.3.4 Undervoltage Protection (UVLO)
- 7.3.5 Reverse Polarity Protection
- 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
- 7.3.7 TPS48100-Q1 as a Simple Gate Driver
- 7.4 Device Functional Modes
- 8 Application and Implementation
- 9 Device and Documentation Support
- 10Revision History
- 11Mechanical, Packaging, and Orderable Information
7.3.3.1 Short-Circuit Protection With Auto-Retry
The CTMR programs the short-circuit protection delay (tSC) and auto-retry time (tRETRY). Once the voltage across CS+ and CS– exceeds the set point, the CTMR starts charging with 80μA pull-up current.
After CTMR charges to V(TMR_SC), G1PD pulls low to SRC and FLT asserts low providing warning on impending FET turn OFF. Post this event, the auto-retry behavior starts. The CTMR capacitor starts discharging with 2.5µA pulldown current. After the voltage reaches V(TMR_LOW) level, the capacitor starts charging with 2.2µA pullup. After 32 charging-discharging cycles of CTMR the FET turns ON back and FLT de-asserts.
The device retry time (tRETRY) is based on CTMR for the first time as per Equation 7 .
Use Equation 6 to calculate the CTMR capacitor to be connected across TMR and GND.
Where,
ITMR is internal pull-up current of 80μA.
tSC is desired short-circuit response time.
The fastest tSC is with no CTMR cap connected.
If the short-circuit pulse duration is below tSC then the FET remains ON and CTMR gets discharged using internal pull down switch.
Figure 7-8 Short-Circuit Protection With Auto-Retry