ZHCSQE1 January   2024 TPS4810-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Charge Pump and Gate Driver Output (VS, G1PU, G1PD, G2, BST, SRC)
      2. 7.3.2 Capacitive Load Driving Using FET Gate (G1PU, G1PD) Slew Rate Control
      3. 7.3.3 Short-Circuit Protection
        1. 7.3.3.1 Short-Circuit Protection With Auto-Retry
        2. 7.3.3.2 Short-Circuit Protection With Latch-Off
      4. 7.3.4 Undervoltage Protection (UVLO)
      5. 7.3.5 Reverse Polarity Protection
      6. 7.3.6 Short-Circuit Protection Diagnosis (SCP_TEST)
      7. 7.3.7 TPS48100-Q1 as a Simple Gate Driver
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Application Limitations
        1. 8.1.1.1 Short-Circuit Protection Delay
        2. 8.1.1.2 Short-Circuit Protection Threshold
    2. 8.2 Typical Application: Circuit Breaker in Battery Management System (BMS) using Low Side Current Sense
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 接收文档更新通知
    2. 9.2 支持资源
    3. 9.3 Trademarks
    4. 9.4 静电放电警告
    5. 9.5 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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机械数据 (封装 | 引脚)
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订购信息

4 Pin Configuration and Functions

GUID-20240108-SS0I-HF2Z-DNLD-V2GSFVPV2NVZ-low.svg Figure 4-1 DGX Package, 19-Pin VSSOP (Top View)
Table 4-1 Pin Functions
PINTYPE(1)DESCRIPTION
NAMENO.
EN/UVLO1I

EN/UVLO Input. A voltage on this pin above 1.24V enables normal operation. Forcing this pin below 0.3V shuts down the device reducing quiescent current to approximately 1.5µA. Optionally connect to the input supply through a resistive divider to set the undervoltage lockout.

When EN/UVLO is left floating an internal pull down of 100nA pulls EN/UVLO low and keeps the device in shutdown state.

INP2

2I

Input signal for external charge FET control. CMOS compatible input reference to GND that sets the state of G2 pin.

INP2 has an internal weak pull down of 100nA to GND to keep G2 pulled to SRC when INP2 is left floating.

INP1

3

I

Input signal for external discharge FET control. CMOS compatible input reference to GND that sets the state of G1PD and G1PU pins.

INP1 has an internal weak pull down of 100nA to GND to keep G1PD pulled to SRC when INP1 is left floating.

N.C

4

—No connect.
FLT

5

OOpen drain fault output. This pin asserts low during short circuit fault, charge pump UVLO, input UVLO, and during SCP comparator diagnosis. If FLT feature is not desired then connect it to GND.
GND6GConnect GND to system ground.
CS_SEL7

I

Current sense select input. Connect this pin to ground to activate high side current sense. Drive this pin to > 2V to activate low side current sensing.

CS_SEL has an internal weak pull down of 100nA to GND.

ISCP8I

Short circuit detection setting. A resistor across ISCP to GND sets the short circuit current comparator threshold.

If short-circuit protection feature is not desired then connect CS+, CS–, and VS pins together. Also connect ISCP and TMR pins to GND.

TMR9IFault timer input. A capacitor across TMR pin to GND sets the times for fault turn-off.
Leave it open for fastest setting. Leave this pin open for fastest response setting. If short-circuit protection feature is not desired then connect CS+, CS–, and VS pins together. Also, connect ISCP and TMR pins to GND.
SCP_TEST10I

Internal short circuit comparator (SCP) diagnosis input.

When SCP_TEST is driven low to high with INP1 pulled high, the internal SCP comparator operation is checked. FLT goes low and G1PD gets pulled to SRC if SCP comparator is functional.

Connect SCP_TEST pin to GND if this feature is not desired.

SCP_TEST has an internal weak pull down of 100nA to GND.

G211O

Charging FET gate drive output. It has 1.69A peak source and 2A sink capacity. Leave the G2 pin floating if the G2 drive functionality is unused.

BST12OHigh side bootstrapped supply. An external capacitor with a minimum value of > Qg(tot) of the external FET must be connected between this pin and SRC.
SRC13OSource connection of the external FET.
G1PD14OHigh current gate driver pull-down. This pin pulls down to SRC. For the fastest turn-off, tie this pin directly to the gate of the external high side MOSFET.
G1PU15OHigh current gate driver pull-up. This pin pulls up to BST. Connect this pin to G1PD for maximum gate drive transition speed. A resistor can be connected between this pin and the gate of the external MOSFET to control the in-rush current during turn-on.
CS–17ICurrent sense negative input
CS+18ICurrent sense positive input.

N.C

19—

No connect.

VS20PSupply pin of the controller.
(1) I = Input, O = Output, I/O = Input and Output, P = Power, G = Ground
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